EM357-MOD-LR-ANT-TG Ember, EM357-MOD-LR-ANT-TG Datasheet - Page 43

• Manufacturer Part Number: EM357-MOD-LR-ANT-TG
• Description: MODULE EM357 PA/LNA W/ANT TG
• Manufacturer: Ember

Specifications of EM357-MOD-LR-ANT-TG

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 25mA
• Current - Transmitting: 42mA
• Data Interface: PCB, Surface Mount
• Memory Size: 192kB Flash, 12kB RAM
• Antenna Connector: On-Board, Chip
• Operating Temperature: -40°C ~ 85°C
• Package / Case: Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Applications: -
• Sensitivity: -
• Other names: 636-1020

6.2.1.8 Deep Sleep Reset
The Power Management module informs the Reset Generation module of entry into and exit from the deep
sleep states. The deep sleep reset is applied in the following states: before entry into deep sleep, while
removing power from the memory and core domain, while in deep sleep, while waking from deep sleep, and
while reapplying power until reliable power levels have been detect by POR LV.
The Power Management module allows a special emulated deep sleep state that retains memory and core
domain power while in deep sleep.
6.2.2
The EM35x records the last reset condition that generated a restart to the system. The reset conditions
recorded are:
Note: While CPU Lockup is shown as a reset condition in software, CPU Lockup is not specifically a reset
event. CPU Lockup is set to indicate that the CPU entered an unrecoverable exception. Execution stops but a
reset is not applied. This is so that a debugger can interpret the cause of the error. Ember recommends that
in a live application (in other words, no debugger attached) the watchdog be enabled by default so that the
EM35x can be restarted.
6.2.3
The Reset Generation module responds to reset sources and generates the following reset signals:
POR HV
POR LV
nRESET
watchdog
SYSRESETREQ
deep sleep wakeup
option byte error
PORESET
SYSRESET
DAPRESET
PRESET
PRESET
Reset Recording
Reset Generation Module
HV
LV
Reset of the ARM
(Flash Patch and Breakpoint, Data Watchpoint and Trace, Instrumentation Trace
Macrocell, Nested Vectored Interrupt Controller). ARM defines PORESET as the region
that is reset when power is applied.
Reset of the ARM
components, so that a live system can be reset without disturbing the debug
configuration.
Reset to the SWJ’s AHB Access Port (AHB-AP)
Peripheral reset for always-on power domain, for peripherals that are required to retain
their configuration across a deep sleep cycle
Peripheral reset for core power domain, for peripherals that are not required to retain
their configuration across a deep sleep cycle
always-on domain power supply failure
core domain (POR LVcore) or memory domain (POR LVmem) power supply failure
pin reset asserted
watchdog timer expired
software reset by SYSERSETREQ from ARM
wake-up from deep sleep
error check failed when reading option bytes from flash
®
®
Cortex
Cortex
Final
6-5
TM
TM
-M3 CPU and ARM
-M3 CPU without resetting the Core Debug and System Debug
®
Cortex
®
Cortex
TM
-M3 System Debug components
TM
-M3 CPU
EM351 / EM357
120-035X-000G