EM357-MOD-LR-ANT-TG Ember, EM357-MOD-LR-ANT-TG Datasheet - Page 83

• Manufacturer Part Number: EM357-MOD-LR-ANT-TG
• Description: MODULE EM357 PA/LNA W/ANT TG
• Manufacturer: Ember

Specifications of EM357-MOD-LR-ANT-TG

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 25mA
• Current - Transmitting: 42mA
• Data Interface: PCB, Surface Mount
• Memory Size: 192kB Flash, 12kB RAM
• Antenna Connector: On-Board, Chip
• Operating Temperature: -40°C ~ 85°C
• Package / Case: Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Applications: -
• Sensitivity: -
• Other names: 636-1020

1
8.3.3
Characters transmitted and received by the SPI master controller are buffered in transmit and receive FIFOs
that are both 4 entries deep. When software writes a character to the SCx_DATA register, the character is
pushed onto the transmit FIFO. Similarly, when software reads from the SCx_DATA register, the character
returned is pulled from the receive FIFO. If the transmit and receive DMA channels are used, they also write to
and read from the transmit and receive FIFOs.
When the transmit FIFO and the serializer are both empty, writing a character to the transmit FIFO clears the
SC_SPITXIDLE bit in the SCx_SPISTAT register. This indicates that some characters have not yet been
transmitted. If characters are written to the transmit FIFO until it is full, the SC_SPITXFREE bit in the
SCx_SPISTAT register is cleared. Shifting out a character to the MOSI pin sets the SC_SPITXFREE bit in the
SCx_SPISTAT register. When the transmit FIFO empties and the last character has been shifted out, the
SC_SPITXIDLE bit in the SCx_SPISTAT register is set.
Characters received are stored in the receive FIFO. Receiving characters sets the SC_SPIRXVAL bit in the
SCx_SPISTAT register, indicating that characters can be read from the receive FIFO. Characters received while
the receive FIFO is full are dropped, and the SC_SPIRXOVF bit in the SCx_SPISTAT register is set. The receive
FIFO hardware generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error
condition until the receive FIFO is drained. Once the DMA marks a receive error, two conditions will clear the
error indication: setting the appropriate SC_TX/RXDMARST bit in the SCx_DMACTRL register, or loading the
appropriate DMA buffer after it has unloaded.
To receive a character, you must transmit a character. If a long stream of receive characters is expected, a
long sequence of dummy transmit characters must be generated. To avoid software or transmit DMA initiating
these transfers and consuming unnecessary bandwidth, the SPI serializer can be instructed to retransmit the
MST
The notation xxx means that the corresponding column header below is inserted to form the field name.
1
1
1
1
1
SCx_SPICFG
SC_SPIxxx
ORD
Operation
0
0
0
0
1
PHA POL
0
0
1
1
-
1
0
1
0
1
-
Same as above except data is sent LSB first instead of MSB first
Table 8-4. SPI Master Mode Formats
Final
8-8
Frame Formats
EM351 / EM357
120-035X-000G