EM357-MOD-LR-ANT-TG Ember, EM357-MOD-LR-ANT-TG Datasheet - Page 181

• Manufacturer Part Number: EM357-MOD-LR-ANT-TG
• Description: MODULE EM357 PA/LNA W/ANT TG
• Manufacturer: Ember

Specifications of EM357-MOD-LR-ANT-TG

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 25mA
• Current - Transmitting: 42mA
• Data Interface: PCB, Surface Mount
• Memory Size: 192kB Flash, 12kB RAM
• Antenna Connector: On-Board, Chip
• Operating Temperature: -40°C ~ 85°C
• Package / Case: Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Applications: -
• Sensitivity: -
• Other names: 636-1020

10.1.1 GPIO Usage
A GPIO pin used by the ADC as an input or voltage reference must be configured in analog mode by writing 0
to its 4-bit field in the proper GPIO_PxCFGH/L register. Note that a GPIO pin in analog mode cannot be used
for any digital functions, and GPIO_PxIN always reads it as 1. Only certain pins can be configured in analog
mode. These are listed in Table 10-1.
See Chapter 7, GPIO for more information about how to configure GPIO.
10.1.2 Voltage Reference
The ADC voltage reference (VREF), may be internally generated or externally sourced from PB0. If internally
generated, it may optionally be output on PB0. To output the internal VREF on PB0, the ADC must be enabled
(ADC_ENABLE bit set in the ADC_CFG register) and PB0 must be configured in analog mode.
To use an external reference, the Ember software must be called after reset and after waking from deep
sleep. PB0 must also be configured in analog mode using GPIO_PBCFGH[3:0]. See the Ember software
documentation for more information on using an external reference.
10.1.3 Offset/Gain Correction
When a conversion is complete, the 16-bit converted data is processed in several steps by offset/gain
correction hardware:
1. The initial signed ADC conversion result is added to the 16-bit signed (two’s complement) value of the ADC
2. The offset-corrected data is multiplied by the 16-bit ADC gain register, ADC_GAIN, to produce a 16-bit
3. The offset/gain corrected value is divided by two to produce the final result.
ADC_GAIN is an unsigned scaled 16-bit value: ADC_GAIN[15] is the integer part of the gain factor and
ADC_GAIN[14:0] is the fractional part. As a result, ADC_GAIN values can represent gain factors from 0 through
(2 – 2
and in practice is loaded with values within a range of about 0.95 to 1.05.
Analog Signal
ADC0 input
ADC1 input
ADC2 input
ADC3 input
ADC4 input
ADC5 input
VREF input or output
If interrupts will be used, configure the top-level and second-level ADC interrupt bits.
Write the ADC configuration register to define the inputs, sample time, and start the conversions.
offset register (ADC_OFFSET).
signed result. If the product is greater than 0x7FFF (32767), or less than 0x8000 (-32768), it is limited to
that value and the INT_ADCSAT bit is set in the INT_ADCFLAG register.
-15
). Although ADC_GAIN can represent a much greater range, its purpose is to correct small gain error,
Table 10-1. ADC GPIO Pin Usage
Final
10-2
GPIO
PC1
PA4
PA5
PB5
PB6
PB7
PB0
Configuration control
GPIO_PBCFGH[7:4]
GPIO_PBCFGH[11:8]
GPIO_PBCFGH[15:12]
GPIO_PCCFGL[7:4]
GPIO_PACFGH[3:0]
GPIO_PACFGH[7:4]
GPIO_PBCFGL[3:0]
EM351 / EM357
120-035X-000G