EM357-MOD-LR-ANT-TG Ember, EM357-MOD-LR-ANT-TG Datasheet - Page 204

• Manufacturer Part Number: EM357-MOD-LR-ANT-TG
• Description: MODULE EM357 PA/LNA W/ANT TG
• Manufacturer: Ember

Specifications of EM357-MOD-LR-ANT-TG

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 25mA
• Current - Transmitting: 42mA
• Data Interface: PCB, Surface Mount
• Memory Size: 192kB Flash, 12kB RAM
• Antenna Connector: On-Board, Chip
• Operating Temperature: -40°C ~ 85°C
• Package / Case: Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Applications: -
• Sensitivity: -
• Other names: 636-1020

11 Interrupt System
11.1
Nested Vectored Interrupt Controller (NVIC)
The EM35x’s interrupt system is composed of two parts: a standard ARM
Interrupt Controller (NVIC) that provides top-level interrupts, and an Ember proprietary Event Manager (EM)
that provides second-level interrupts. The NVIC and EM provide a simple hierarchy. All second-level interrupts
from the EM feed into top-level interrupts in the NVIC. This two-level hierarchy allows for both fine granular
control of interrupt sources and coarse granular control over entire peripherals, while allowing peripherals to
have their own interrupt vector.
The Nested Vectored Interrupt Controller (NVIC) section provides a description of the NVIC and an overview of
the exception table (ARM nomenclature refers to interrupts as exceptions). The Event Manager section
provides a more detailed description of the Event Manager including a table of all top-level peripheral
interrupts and their second-level interrupt sources.
In practice, top-level peripheral interrupts are only used to enable or disable interrupts for an entire
peripheral. Second-level interrupts originate from hardware sources, and therefore are the main focus of
applications using interrupts.
The ARM
interrupt handling. The NVIC and the processor core interface are closely coupled, which enables low-latency
interrupt processing and efficient processing of late-arriving interrupts. The NVIC also maintains knowledge of
the stacked (nested) interrupts to enable tail-chaining of interrupts.
The ARM
management. In addition to the 10 standard interrupts, it contains 17 individually vectored peripheral
interrupts specific to the EM35x.
The NVIC defines a list of exceptions. These exceptions include not only traditional peripheral interrupts, but
also more specialized events such as faults and CPU reset. In the ARM
considered an exception of the highest priority, and the stack pointer is loaded from the first position in the
NVIC exception table. The NVIC exception table defines all exceptions and their position, including peripheral
interrupts. The position of each exception is important since it directly translates to the location of a 32-bit
interrupt vector for each interrupt, and defines the hardware priority of exceptions. Each exception in the
table is a 32-bit address that is loaded into the program counter when that exception occurs. Table 11-1 lists
the entire exception table. Exceptions 0 (stack pointer) through 15 (SysTick) are part of the standard ARM
Cortex
the EM35x peripherals. The peripheral interrupts are listed in greater detail in Table 11-2.
TM
-M3 NVIC, while exceptions 16 (Timer 1) through 32 (Debug) are the peripheral interrupts specific to
®
®
Cortex
Cortex
TM
TM
-M3 Nested Vectored Interrupt Controller (NVIC) facilitates low-latency exception and
-M3 NVIC contains 10 standard interrupts that are related to chip and CPU operation and
Final
11-1
®
Cortex
®
Cortex
TM
EM351 / EM357
-M3 NVIC, a CPU reset event is
TM
-M3 Nested Vectored
120-035X-000G
®