AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 10

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
TIME DURATION OF DIGITAL FUNCTIONS
Table 13.
Parameter
TIME DURATION OF DIGITAL FUNCTIONS
DIGITAL PLL
Table 14.
Parameter
DIGITAL PLL
1
2
3
DIGITAL PLL LOCK DETECTION
Table 15.
Parameter
PHASE LOCK DETECTOR
FREQUENCY LOCK DETECTOR
HOLDOVER SPECIFICATIONS
Table 16.
Parameter
HOLDOVER SPECIFICATIONS
f
f
f
PFD
S
REF
EEPROM-to-Register Download Time
Register-to-EEPROM Upload Time
Minimum Power-Down Exit Time
Maximum Time from Assertion of the RESET
Phase-Frequency Detector (PFD)
Loop Bandwidth
Phase Margin
Reference Input (R) Division Factor
Integer Feedback (S) Division Factor
Fractional Feedback Divide Ratio
Threshold Programming Range
Threshold Resolution
Threshold Programming Range
Threshold Resolution
Frequency Accuracy
is the sample rate of the output DAC.
is the frequency of the active reference; R is the frequency division factor determined by the R-divider.
is the frequency at the input to the phase-frequency detector.
pin to the M0 to M7 Pins Entering High
Impedance State
Input Frequency Range
Min
1
0.001
30
1
8
0
Min
Min
0.001
0.001
Min
Typ
1
1
Typ
<0.01
Typ
Rev. A | Page 10 of 112
Max
65.5
16,700
Max
Typ
25
200
10.5
45
Max
10
10
89
2
2
0.999
30
30
7
5
Unit
ns
ps
ns
ps
Unit
ppm
Unit
Hz
Hz
Degrees
Max
Reference-to-feedback period difference
Test Conditions/Comments
Maximum f
Programmable design parameter; maximum
f
Programmable design parameter
1, 2, …, 1,073,741,824
8, 9, …, 1,073,741,824
Maximum value: 1022/1023.
Test Conditions/Comments
Test Conditions/Comments
Excludes frequency drift of SYSCLK source;
excludes frequency drift of input reference prior
to entering holdover
LOOP
Unit
ms
ms
μs
ns
= f
REF
/(20R)
PFD
Test Conditions/Comments
Using default EEPROM storage
sequence (see Register 0E10 to
Register 0E3F)
Using default EEPROM storage
sequence (see Register 0E10 to
Register 0E3F
Dependent on loop-filter bandwidth
1
: f
3
S
/100
2