AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 40

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
Super-Nyquist Operation
Typically, the maximum usable frequency at the DAC output is
about 45% of the system clock frequency. However, because it is
a sampled DAC, its output spectrum contains Nyquist images.
Of particular interest are the images appearing in the first Nyquist
zone (50% to 100% of the system clock frequency). Super-
Nyquist operation takes advantage of these higher frequencies,
but this implies that the CLKINx input operates in excess of
500 MHz, which is outside of its default operating limits.
The CLKINx receiver actually consists of two separate receivers:
the default receiver and an optional high frequency receiver,
which handles input signals up to 800 MHz. To select the high
frequency receiver, write a Logic 1 to Register 0400, Bit 4.
Super-Nyquist operation requires a band-pass filter at the DAC
output instead of the usual low-pass reconstruction filter. Super-
Nyquist operation is viable as long as the image frequency does
not exceed the 800 MHz input range of the receiver. Furthermore,
to provide acceptable jitter performance, which is a consideration
for image signals with low amplitude, the signal at the CLKINx
input must meet the minimum slew rate requirements.
Clock Dividers
The output clock distribution dividers are referred to as Q0 to Q3,
corresponding to the OUT0 to OUT3 output channels, respectively.
Each divider is programmable with 30 bits of division depth. The
actual divider ratio is one more than the programmed register
value; therefore, a register value of 3, for example, results in a
divide ratio of 4. Thus, each divider offers a range of divide
ratios from 1 to 2
With an even divide ratio, the output signal always exhibits a
50% duty cycle. When the clock divider is bypassed (a divide
ratio of 1), the output duty cycle is the same as the input duty
cycle. Odd output divide ratios (excluding 1) exhibit automatic
duty cycle correction given by
where N (which must be an odd number) is the divide ratio and
X is the normalized fraction of the high portion of the input
period (that is, 0 < X < 1).
For example, if N = 5 and the input duty cycle is 20% (X = 0.2),
then the output duty cycle is 44%. Note that, when the user programs
an output as noninverting, then the device adjusts the falling
edge timing to accomplish the duty cycle correction. Conversely,
the device adjusts the rising edge timing for an inverted output.
Output Power-Down
Each of the output channels offers independent control of
power-down functionality via the distribution settings register
(Address 0400). Each output channel has a dedicated power-
down bit for powering down the output driver. However, if all
four outputs are powered down, the entire distribution output
enters a deep sleep mode.
Output
Duty
30
Cycle
(1 to 1,073,741,824).
N
2
2
N
X
1
Rev. A | Page 40 of 112
Even though each channel has a channel power-down control
signal, it may sometimes be desirable to power down an output
driver while maintaining the divider’s synchronization with the
other channel dividers. This is accomplished by either of the
following methods:
Output Enable
Each of the output channels offers independent control of enable/
disable functionality via the distribution enable register
(Address 0401). The distribution outputs use synchronization
logic to control enable/disable activity to avoid the production
of runt pulses and ensure that outputs with the same divide
ratios become active/inactive in unison.
Output Mode
The user has independent control of the operating mode of
each of the four output channels via the distribution channel
modes register (Address 0404 to Address 0407). The operating
mode control includes
The three least significant bits of each of the four distribution
channel mode registers comprise the mode bits. The mode
value selects the desired logic family and pin functionality of an
output channel, as given in Table 23.
Table 23. Output Channel Logic Family and Pin
Functionality
Mode Bits [2:0]
000
001
010
011
100
101
110
111
Regardless of the selected logic family, each is capable of dc
operation. However, the upper frequency is limited by the load
conditions, drive strength, and impedance matching inherent in
each logic family. Practical limitations set the maximum CMOS
frequency to approximately 250 MHz, whereas LVPECL and
LVDS are capable of 725 MHz.
In CMOS mode, use the divider output enable control bit
to stall an output. This provides power savings while
maintaining dc drive at the output.
In LVDS/LVPECL mode, place the output in tristate mode
(this works in CMOS mode as well).
Logic family and pin functionality
Output drive strength
Output polarity
Logic Family and Pin Functionality
CMOS (both pins)
CMOS (positive pin); tristate (negative pin)
Tristate (positive pin); CMOS (negative pin)
Tristate (both pins)
LVDS
LVPECL
Unused
Unused