AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 61

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Addr
0210
0211
0212
0213
0214
0300
0301
0302
0303
0304
0305
0306
0307
0308
0309
030A
030B
030C
030D
030E
030F
0310
0311
0312
0313
0314
0315
0316
0317
0318
0319
031A
031B
0400
0401
0402
0403
0404
0405
Opt
C
C
C
S
S
C
C
C
C
C
C
A, C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
S
S
S
C
S
S
Name
Watchdog
timer
DAC current
Free running
frequency
tuning word
Update TW
Pull-in
range limits
Open loop
phase offset
Closed loop
phase offset
Phase slew
limit
History
accumulation
timer
History
mode
Distribution
settings
Distribution
enable
Distribution
synchroniza-
tion
Automatic
synchroniza-
tion
Distribution
channel
modes
D7
Ref DD
new profile
Watchdog timer (ms) [15:0] [up to 65.5 sec]
DAC full-scale current [7:0]
DAC
shutdown
Free running frequency tuning word [47:0]
Unused
Pull-in range lower limit [23:0]
Pull-in range upper limit [23:0]
DDS phase offset word [15:0]
Fixed phase lock offset [39:0] (picoseconds; signed)
Incremental phase lock offset step size [15:0]
(picoseconds)
Phase slew rate limit [15:0] (ns/sec)
History accumulation timer [23:0] (milliseconds)
Unused
Unused
Unused
Unused
Unused
Unused
Unused
D6
Ref DD
validated
Unused
External
distribution
resistor
D5
Ref DD
fault
cleared
Sync source [1:0]
OUT0
CMOS
phase
invert
OUT1
CMOS
phase
invert
Rev. A | Page 61 of 112
D4
Ref DD
fault
Single
sample
fallback
Receiver
mode
OUT0
polarity
invert
OUT1
polarity
invert
Clock distribution output
DPLL
D3
Ref D
new
profile
Persistent
history
OUT3
power-
down
OUT3
enable
OUT3
sync mask
OUT0
drive
strength
OUT1
drive
strength
Incremental average [2:0]
D2
Ref D
validated
OUT2
power-
down
OUT2
enable
OUT2
sync mask
OUT0 mode
OUT1 mode
D1
Ref D
fault
cleared
DAC full-scale current
[9:8]
OUT1
power-
down
OUT1
enable
OUT1
sync mask
Automatic sync mode
[1:0]
D0
Ref D
fault
Update TW
OUT0
power-
down
OUT0
enable
OUT0
sync mask
AD9548
Def
00
00
00
FF
01
00
00
00
00
00
00
00
00
00
00
FF
FF
FF
00
00
00
00
00
00
00
E8
03
00
00
30
75
00
00
00
00
00
00
03
03