AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 71

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SYSTEM CLOCK (REGISTER 0100 TO REGISTER 0108)
Table 42. Charge Pump and Lock Detect Control
Address
0100
Table 43. N Divider
Address
0101
Table 44. SYSCLK Input Options
Address
0102
[7]
[6]
[5:3]
[2]
[1:0]
[7:0]
[7]
[6]
[5:4]
[3]
[2]
[1:0]
Bits
Bits
Bits
External loop filter
enable
Charge pump mode
Charge pump current
Lock detect timer
disable
Lock detect timer
N-divider
Unused
M-divider reset
M-divider
PLL enable
System clock source
Bit Name
Bit Name
Bit Name
2× frequency
multiplier enable
Description
Enables use of an external SYSCLK PLL loop filter
0 (default) = internal loop filter
1 = external loop filter
Charge pump current control
0 (default) = automatic
1 = manual
Selects charge pump current when Bit 6 = 1
000 = 125 μA
001 = 250 μA
010 = 375 μA
011 (default) = 500 μA
100 = 625 μA
101 = 750 μA
110 = 875 μA
111 = 1000 μA
Enable the SYSCLK PLL lock detect timer
0 (default) = enable
1 = disable
Select lock detect timer depth
00 (default) = 128
01 = 256
10 = 512
11 = 1024
Description
System clock PLL feedback divider value: 6 ≤ N ≤ 255 (default = 0x28 = 40)
Description
Reset the M-divider
0 = normal operation
1 (default) = reset
When not using the M-divider, program this bit to Logic 1.
System clock input divider
00 (default) = 1
01 = 2
10 = 4
11 = 8
Enable the 2× frequency multiplier
0 (default) = disable
1 = enable
Enable the SYSCLK PLL
0 = disable
1 (default) = enable
Input mode select for SYSCLKx pins
00 = crystal resonator
01 (default) = low frequency clock source
10 = high frequency (direct) clock source
11 = input receiver power-down
Rev. A | Page 71 of 112
AD9548