AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 62

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AD9548/PCBZ

Manufacturer Part Number
AD9548/PCBZ
Description
Clock Generator Evaluation Board
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9548/PCBZ

Silicon Manufacturer
Analog Devices
Application Sub Type
Network Clock Generator/Synchronizer
Kit Application Type
Clock & Timing
Silicon Core Number
AD9548
Kit Contents
Board
Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
AD9548
Primary Attributes
62.5 ~ 450 MHz Output Frequency
Secondary Attributes
SPI and I2C Compatible Control Port
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9548
Addr
0406
0407
0408
0409
040A
040B
040C
040D
040E
040F
0410
0411
0412
0413
0414
0415
0416
0417
0500
0501
0502
0503
0504
0505
0506
0507
0600
0601
0602
0603
0604
0605
0606
0607
0608
0609
060A
060B
060C
060D
Opt
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
C
C
C
C
C
Name
Distribution
channel
dividers
Reference
power-down
Reference
logic family
Manual
reference
profile
selection
Phase build-
out switching
Priorities
Reference
period
Tolerance
D7
Unused
Unused
Q0 [23:0]
Unused
Q1 [23:0]
Unused
Q2 [23:0]
Unused
Q3 [23:0]
Unused
Ref DD
power-
down
Ref BB logic family [1:0]
Ref DD logic family [1:0]
Enable Ref
AA manual
profile
Enable Ref
BB Manual
Profile
Enable Ref
CC Manual
Profile
Enable Ref
DD Manual
Profile
Unused
Phase lock
scale
Nominal period (femtoseconds) [47:0] (up to 1.125 sec)
Unused
Inner tolerance (1/tolerance) [15:0] (removes fault status; 10% down to 1 ppm)
Unused
Outer tolerance (1/tolerance) [15:0] (indicates fault status; 10% down to 1 ppm)
Unused
Ref D
power-
down
Unused
D6
Ref AA manual profile [2:0]
Ref BB manual profile [2:0]
Ref CC manual profile [2:0]
Ref DD manual profile [2:0]
D5
OUT2
CMOS
phase
invert
OUT3
CMOS
phase
invert
Q0 [29:24]
Q1 [29:24]
Q2 [29:24]
Q3 [29:24]
Ref CC
power-
down
Ref B logic family [1:0]
Ref D logic family [1:0]
Promoted priority [2:0]
Rev. A | Page 62 of 112
Ref C
power-
down
D4
OUT2
polarity
invert
OUT3
polarity
invert
Reference inputs
Profile 0
Ref BB
power-
down
Ref AA logic family [1:0]
Ref CC Logic Family [1:0]
Enable Ref
A manual
profile
Enable Ref
B manual
profile
Enable Ref
C manual
profile
Enable Ref
D manual
profile
D3
Inner tolerance [19:16]
Outer tolerance [19:16]
OUT2
drive
strength
OUT3
drive
strength
Ref B
power-
down
D2
OUT2 mode
OUT3 mode
Ref A manual profile [2:0]
Ref B manual profile [2:0]
Ref C manual profile [2:0]
Ref D manual profile [2:0]
Phase master threshold priority [2:0]
Selection priority [2:0]
D1
Ref AA
power-
down
Ref A logic family [1:0]
Ref C Logic Family [1:0]
Nominal period [49:48]
D0
Ref A
power-
down
Def
00
00
00
00
00
00
00
03
03
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

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