AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 104

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
Table 151. EEPROM Storage Sequence for Operational Control Settings
Address
0E2F
0E30
0E31
0E32
Table 152. EEPROM Storage Sequence for End of Data
Address
0E33
Bits
[7:0]
[7:0]
[7:0]
[7:0]
Bits
[7:0]
Operational controls
Operational controls
I/O update
Bit Name
Bit Name
End of data
Description
The default value of this register is 0x10, which the controller interprets as a data
instruction. Its decimal value is 16, which this tells the controller to transfer 17
bytes of data (16 + 1) beginning at the address specified by the next two bytes. The
controller stores 0x10 in the EEPROM and increments the EEPROM address pointer.
The default value of these two registers is 0x0A00. Note that Register 0E30 and
Register 0E31 are the most significant and least significant bytes of the target
address, respectively. Because the previous register contains a data instruction,
these two registers define a starting address (in this case, 0x0A00). The controller
stores 0x0A00 in the EEPROM and increments the EEPROM pointer by 2. It then
transfers 17 bytes from the register map (beginning at Address 0x0A00) to the
EEPROM and increments the EEPROM address pointer by 18 (17 data bytes and
one checksum byte). The 17 bytes transferred correspond to the operational
controls parameters in the register map.
The default value of this register is 0x80, which the controller interprets as an I/O
update instruction. The controller stores 0x80 in the EEPROM and increments the
EEPROM address pointer.
Description
The default value of this register is 0xFF, which the controller interprets as an end
instruction. The controller stores this instruction in the EEPROM, resets the EEPROM
address pointer, and enters an idle state. Note that, if this were a pause rather than
an end instruction, the controller actions would be the same except that the
controller would not reset the EEPROM address pointer.
Rev. A | Page 104 of 112