AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 6

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
Parameter
SYSTEM CLOCK PLL ENABLED
DISTRIBUTION CLOCK INPUTS (CLKINP/CLKINN)
Table 7.
Parameter
DISTRIBUTION CLOCK INPUTS (CLKINP/CLKINN)
PLL Output Frequency Range
Phase-Frequency Detector (PFD) Rate
Frequency Multiplication Range
VCO Gain
High Frequency Path
Low Frequency Path
Crystal Resonator Path
Input Frequency Range
Minimum Slew Rate
Common-Mode Voltage
Differential Input Voltage Sensitivity
Differential Input Power Sensitivity
Input Capacitance
Input Resistance
Input Frequency Range
Minimum Input Slew Rate
Frequency Divider Range
Common-Mode Voltage
Differential Input Voltage Sensitivity
Input Capacitance
Input Resistance
Input Frequency Range
Minimum Input Slew Rate
Common-Mode Voltage
Differential Input Voltage Sensitivity
Input Capacitance
Input Resistance
Crystal Resonator Frequency Range
Maximum Crystal Motional Resistance
Min
900
6
100.1
200
1
100
3.5
50
100
10
Min
62.5
75
100
−15
Typ
70
1
3
2.5
1.2
3
4
Rev. A | Page 6 of 112
Typ
700
3
5
Max
1000
150
255
500
8
100
50
100
Max
500
Unit
MHz
MHz
MHz/V
MHz
V/μs
V
mV p-p
pF
kΩ
MHz
V/μs
V
mV p-p
pF
kΩ
MHz
Ω
mV
Unit
MHz
V/μs
mV p-p
dBm
pF
kΩ
Test Conditions/Comments
Assumes valid system clock and PFD rates
Minimum limit imposed for jitter
performance
Binary steps (M = 1, 2, 4, 8)
Internally generated
Minimum voltage across pins required to
ensure switching between logic states;
the instantaneous voltage on either pin
must not exceed the supply rails; can
accommodate single-ended input by ac
grounding unused input
Single-ended, each pin
Minimum limit imposed for jitter
performance
Internally generated
Minimum voltage across pins required to
ensure switching between logic states;
the instantaneous voltage on either pin
must not exceed the supply rails; can
accommodate single-ended input by ac
grounding unused input
Single-ended, each pin
Fundamental mode, AT cut
See the System Clock Inputs section for
recommendations
Test Conditions/Comments
Minimum limit imposed for jitter
performance.
Internally generated.
Capacitive coupling required; can
accommodate single-ended input
by ac grounding unused input; the
instantaneous voltage on either pin
must not exceed the supply rails.
The same as voltage sensitivity but
specified as power into a 50 Ω load.
Each pin has a 2.5 kΩ internal dc-
bias resistance.