AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 43

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The deterministic delay, expressed as t
equation is a function of the frequency division factor (Q
the channel divider associated with the zero-delay channel.
In addition to deterministic delay, there is random delay (t
associated with the propagation of the reference signal through
the input reference receiver, as well as the propagation of the
clock signal through the clock distribution logic. The total delay is
The user can compensate for t
controls of the device to move the edge timing of the
distribution output signal relative to the input reference edge.
One method is to use the open-loop phase offset registers
(Address 030D to Address 030E) for timing adjustment.
However, be sure to use sufficiently small phase increments to
make the adjustment. Too large a phase step can result in the
clock distribution logic missing a CLKINx edge, thus ruining the
edge alignment process. The appropriate phase increment
depends on the transient response of any external circuitry
connected between the DACOUTx and CLKINx pins.
t
or
t
t
LATENCY
LATENCY
DELAY
= t
= (Q
= (Q
LATENCY
n
n
+ 4) × t
+ 5) × t
+ t
PROP
CLK_IN
CLK_IN
DELAY
by using the phase offset
LATENCY
in the following
n
) of
PROP
Rev. A | Page 43 of 112
)
The other method is to use the closed-loop phase offset registers
(Address 030F to Address 0315) for timing adjustment. However,
be sure to use a sufficiently small phase vs. time profile. Changing
the phase too quickly can cause the DPLL to lose lock, thus
ruining the edge alignment process. Note that the AD9548
phase slew limit register (Address 0316 to Address 0317) can be
used to limit the rate of change of phase automatically, thereby
mitigating the potential loss-of-lock problem.
To guarantee synchronization of the output dividers, it is
important to make any edge timing adjustments after the
synchronization event. Furthermore, when making timing
adjustments, the distribution outputs can be disabled and then
enabled after the adjustment is complete. This prevents the
device from generating output clock signals during the timing
adjustment process.
Note that the form of zero-delay synchronization described here
does not track propagation time variations within the distribution
clock input path or the reference input path (on or off chip)
over temperature, supply, and so on. It is strictly a one-time
synchronization event.
Synchronization Mask
Each output channel has dedicated synchronization mask bits
(Register 0402, Bits[3:0]). When the mask bit associated with a
particular channel is set, then that channel does not respond to
the synchronization signal. This allows the device to operate
with the masked channels active and the unmasked channels
stalled while they wait for a synchronization pulse.
AD9548