AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 35

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDS Phase Offset
The relative phase of the sinusoid generated by the DDS is
numerically controlled by adding a phase offset word to the output
of the DDS accumulator. This is accomplished via the open loop
phase offset register (Address 030D to Address 030E), which is
a programmable 16-bit value (Δphase). The resulting phase offset,
ΔΦ (in radians), is given by
Phase offset and relative time offset are directly related. The
time offset is ( phase/2
output frequency of the DDS (in hertz).
DAC Output
The output of the digital core of the DDS is a time series of
numbers representing a sinusoidal waveform. The DAC
translates the numeric values to an analog signal. The DAC
output signal appears at two pins that constitute a balanced
current source architecture (see Figure 43).
The value of I
current word in the DAC current register (Address 0213 to
Address 0214). The value of the 10-bit word (I
according to the following formula:
TUNING WORD PROCESSING
The frequency tuning words that dictate the output frequency
of the DDS come from one of three sources (see Figure 44).
The free running frequency tuning word register
The output of the digital loop filter
The output of the tuning word history processor
I
FS
Φ
DACOUTP
I
FS
(
2
120
2
CODE
14
I
SCALE
FS
⎛
⎜
⎝
– 1
is programmable via the 10-bit DAC full-scale
μA
18
)
phase
2
GND
50Ω
16
Figure 43. DAC Output Pins
10
72
16
⎞
⎟
⎠
)/f
16
DDS
CURRENT
CONTROL
CURRENT
3
MIRROR
SWITCH
SWITCH
ARRAY
14
AVDD3
CODE
21
22
(in seconds), where f
I
SCALE
I
FS
GND
50Ω
19
I
FS
SCALE
DACOUTN
(1–
2
CODE
) sets I
14
DDS
– 1
is the
)
FS
Rev. A | Page 35 of 112
When the DPLL is in free-run mode, the DDS tuning word is
the value stored in the free running frequency tuning word
register (Address 0300 to Address 0305). When the DPLL is
operating normally (closed loop), the DDS tuning word comes
from the output of the digital loop filter, which changes
dynamically in order to maintain phase lock with the input
reference signal (assuming that the device has not performed an
automatic switch to holdover mode). When the DPLL is in
holdover mode, the DDS tuning word depends on a historical
record of past tuning words during the time that the DPLL
operated in closed-loop mode.
However, regardless of the operating mode, the DDS output
frequency is ultimately subject to the boundary conditions
imposed by the frequency clamp logic, as explained in the
Frequency Clamp section.
Frequency Clamp
The user controls the frequency clamp boundaries via the pull-
in range limits registers (Address 0307 to Address 030C). These
registers allow the user to fix the DDS output frequency
between an upper and lower bound with a granularity of 24 bits.
Note that these upper and lower bounds apply regardless of the
frequency tuning word that appears at the input to the DDS.
The register value relates to the absolute upper or lower
frequency bound (f
Where N is the value stored in the upper- or lower-limit
register, and f
Even though the frequency clamp limits put a bound on the
DDS output frequency, the DPLL is still free to steer the DDS
frequency within the clamp limits. The default register values
set the clamp range from 0 Hz (dc) to f
the frequency clamp functionality until the user alters the
register values.
Frequency Tuning Word History
The AD9548 has the ability to track the history of the tuning
word samples generated by the DPLL digital loop filter output.
It does so by periodically computing the average tuning word
value over a user-specified interval. The user programs the
interval via the 24-bit history accumulation timer register
(Address 0318 to Address 031A). This 24-bit value represents
a time interval (T
a maximum of 4:39:37.215 (hr:min:sec).
TUNING WORD
TUNING WORD
TUNING WORD
f
FROM DIGITAL
CLAMP
FREE-RUN
LOOP FILTER
HISTORY
UPDATE
= f
S
S
× (N/2
is the system sample rate.
AVG
Figure 44. Tuning Word Processing
CLAMP
) in milliseconds that extends from 1 ms to
CONTROL
24
ROUTING
TUNING
WORD
)
) as
TUNING
LOWER
WORD
TUNING WORD
PROCESSOR
HISTORY
TUNING
CLAMP
WORD
S
, effectively eliminating
TUNING
UPPER
WORD
AD9548
TO DDS