AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 93

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 119. Loop Mode
Address
0A01
Table 120. Cal/Sync
Address
0A02
[7]
[6]
[5]
[4:3]
[2:0]
Bits
[7:2]
[1]
[0]
Bits
Bit Name
unused
Sync distribution
Calibrate system
clock
Bit Name
Unused
User holdover
User freerun
User selection mode
User reference
selection
Description
Force the device into holdover mode.
0 (default) = normal operation.
1 = force device into holdover mode.
The device behaves as though all input references are faulted.
Force the device into free-run mode.
0 (default) = normal operation.
1 = force device into free-run mode.
The free running frequency tuning word register specifies the DDS output frequency.
Note that, when the user freerun bit is set, it overrides the user holdover bit.
Select the operating mode of the reference switching state machine.
00 (default) = automatic mode. The fully automatic priority-based algorithm selects
the active reference (Bits[2:0] are ignored).
01 = fallback mode. The active reference is the user reference (Bits[2:0]) as long as it is
valid. Otherwise, use the fully automatic priority-based algorithm to select the active
reference.
10 = holdover mode. The active reference is the user reference (Bits[2:0]) as long as it
is valid. Otherwise, enter holdover mode.
11 = manual mode. The active reference is always the user reference (Bits[2:0]). When
using manual mode, be sure that the reference declared as the user reference
(Bits[2:0]) is programmed for manual reference-to-profile assignment in the
appropriate manual reference profile selection register (Address 0503 to Address
0506).
Input reference when user selection mode = 01, 10, or 11.
000 (default) = Input Reference A
001 = Input Reference AA
010 = Input Reference B
011 = Input Reference BB
100 = Input Reference C
101 = Input Reference CC
110 = Input Reference D
111 = Input Reference DD
Description
Setting this bit (default = 0) initiates synchronization of the clock distribution output.
While this bit = 1, the clock distribution output stalls. Synchronization occurs on the
1 to 0 transition of this bit.
Setting this bit (default = 0) initiates an internal calibration of the SYSCLK PLL
(assuming it is enabled). The calibration routine automatically selects the proper VCO
frequency band and signal amplitude. The internal system clock stalls during the
calibration procedure, disabling the device until the calibration is complete (a few
milliseconds).
Rev. A | Page 93 of 112
AD9548