AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 12

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
Parameter
TIMING
1
JITTER GENERATION
Table 19.
Parameter
JITTER GENERATION
C
b
SCL Clock Rate
Bus-Free Time Between a Stop and Start
Repeated Start Condition Setup Time,
Repeated Hold Time Start Condition, t
Stop Condition Setup Time, t
Low Period of the SCL Clock, t
High Period of the SCL Clock, t
SCL/SDA Rise Time, t
SCL/SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
Capacitive Load for Each Bus Line, C
f
f
f
REF
REF
REF
is the capacitance (pF) of a single bus line.
Condition, t
t
Bandwidth: 100 Hz to 61 MHz
Bandwidth: 5 kHz to 20 MHz
Bandwidth: 20 kHz to 80 MHz
Bandwidth: 50 kHz to 80 MHz
Bandwidth: 4 MHz to 80 MHz
Bandwidth: 100 Hz to 77 MHz
Bandwidth: 5 kHz to 20 MHz
Bandwidth: 20 kHz to 80 MHz
Bandwidth: 50 kHz to 80 MHz
Bandwidth: 4 MHz to 80 MHz
Bandwidth: 100 Hz to 77 MHz
Bandwidth: 5 kHz to 20 MHz
Bandwidth: 20 kHz to 80 MHz
Bandwidth: 50 kHz to 80 MHz
Bandwidth: 4 MHz to 80 MHz
SU; STA
= 1 Hz
= 8 kHz
= 19.44 MHz
1
; f
1
; f
DDS
DDS
BUF
= 122.88 MHz
1
= 155.52 MHz
; f
HD; DAT
SU; DAT
DDS
F
R
= 155.52 MHz
SU; STO
LO
2
HI
2
; f
; f
LOOP
LOOP
2
b
= 0.01 Hz
; f
1
= 100 Hz
LOOP
HD; STA
= 1 kHz
3
3
Min
1.3
0.6
0.6
0.6
1.3
0.6
20 + 0.1 C
20 + 0.1 C
100
100
3
Min
Rev. A | Page 12 of 112
b
b
1
1
Typ
0.81
0.73
0.79
0.78
0.37
0.71
0.34
0.43
0.43
0.31
1.05
0.34
0.43
0.43
0.32
Typ
Max
Max
400
300
300
400
Unit
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
pF
Test Conditions/Comments
f
divider = 1; default SysClk PLL charge pump
current; results valid for LVPECL, LVDS, and
CMOS output logic types
Random jitter
Random jitter
Random jitter
Random jitter
Random jitter
f
f
PLL charge pump current; results valid for
LVPECL, LVDS, and CMOS output logic types
Random jitter
Random jitter
Random jitter
Random jitter
Random jitter
f
f
PLL charge pump current; results valid for
LVPECL, LVDS, and CMOS output logic types
Random jitter
Random jitter
Random jitter
Random jitter
Random jitter
SYSCLK
SYSCLK
S
SYSCLK
S
= 1 GHz
= 1 GHz
= 20 MHz
= 50 MHz
= 50 MHz
Test Conditions/Comments
After this period, the first clock
pulse is generated.
5
5
; Q-divider = 1; default SYSCLK
; Q-divider = 1; default SYSCLK
4
4
4
crystal;
crystal;
OCXO; f
S
= 1 GHz
5
; Q-