AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 94

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
Register 0A03—ResetFunc
Table 121. Reset Functions
Address
0A03
1
Register 0A04 to Register 0A0B—IRQ Clearing
The IRQ clearing registers are identical in format to the IRQ monitor registers (Address 0D02 to Address 0D09). When set to Logic 1, an
IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ
clearing register is an autoclearing register.
Table 122. IRQ Clearing for SYSCLK
Address
0A04
Table 123. IRQ Clearing for Distribution Sync, Watchdog Timer, and EEPROM
Address
0A05
Table 124. IRQ Clearing for the Digital PLL
Address
0A06
All bits in this register are autoclearing.
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Bits
Bits
[7:6]
[5]
[4]
[3:2]
[1]
[0]
Bits
[7:4]
[3]
[2]
[1]
[0]
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
1
Bit Name
Unused
Clear LF
Clear CCI
Clear phase
accumulator
Reset auto sync
Reset TW history
Reset all IRQs
Reset watchdog
Switching
Phase locked
Bit Name
Unused
SYSCLK unlocked
SYSCLK locked
Unused
SYSCLK Cal complete
SYSCLK Cal started
Bit Name
Unused
Distribution sync
Watchdog timer
EEPROM fault
EEPROM complete
Bit Name
Closed
Freerun
Holdover
Freq unlocked
Freq locked
Phase unlocked
Description
Setting this bit (default = 0) clears the digital loop filter (intended as a debug tool).
Setting this bit (default = 0) clears the CCI filter (intended as a debug tool).
Setting this bit (default = 0) clears DDS phase accumulator (not a recommended
action).
Setting this bit (default = 0) resets the automatic synchronization logic
(see Register 0403).
Setting this bit (default = 0) resets the tuning word history logic (part of holdover
functionality).
Setting this bit (default = 0) clears the entire IRQ monitor register (Register 0D02 to
Register 0D09). It is the equivalent of setting all the bits of the IRQ clearing register
(Register 0A04 to Register 0A0B).
Setting this bit (default = 0) resets the watchdog timer (see Register 0211 to Register
0212). If the timer had timed out, it simply starts a new timing cycle. If the timer has
not yet timed out, it restarts at time zero without causing a timeout event.
Continuously resetting the watchdog timer at intervals less than its timeout period
prevents the watchdog timer from generating a timeout event.
Clears switching IRQ
Clears closed IRQ
Clears freerun IRQ
Clears holdover IRQ
Clears frequency unlocked IRQ
Clears frequency locked IRQ
Clears phase unlocked IRQ
Clears phase locked IRQ
Description
Clears SYSCLK unlocked IRQ
Clears SYSCLK locked IRQ
Clears SYSCLK calibration complete IRQ
Clears SYSCLK calibration started IRQ
Description
Description
Clears distribution sync IRQ
Clears watchdog timer IRQ
Clears EEPROM fault IRQ
Clears EEPROM complete IRQ
Rev. A | Page 94 of 112