AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 58

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
I/O PROGRAMMING REGISTERS
The register map spans an address range from 0x0000 through
0x0E3F (0 to 3647, decimal). Each address provides access to 1
byte (eight bits) of data. Each individual register is identified by
its four-digit hexadecimal address (for example, Register 0A10).
In some cases, a group of addresses collectively define a register
(for example, the IRQ mask register consists of Register 0209,
Register 020A, Register 020B, Register 020C, Register 020D,
Register 020E, Register 020F, and Register 0210).
In general, when a group of registers defines a control
parameter, the LSB of the value resides in the D0 position of the
register with the lowest address. The bit weight increases right
to left, from the lowest register address to the highest register
address. For example, the default value of the incremental phase
lock offset step size register (Address 0314 to Address 0315) is
the 16-bit hexadecimal number, 0x03E8 (not 0xE803).
Note that the EEPROM storage sequence registers (Address
0E10 to Address 0E3F) are an exception to the above convention
(see the EEPROM Instructions section).
BUFFERED/ACTIVE REGISTERS
There are two broad categories of registers in the AD9548,
buffered and active (see Figure 65). Buffered registers are those
that can be written to directly from the serial port. They do not
need an I/O update to apply their contents to the internal device
functions. In contrast, active registers require an I/O update to
transfer data between the buffer registers and the internal
device functions. In operation, the user programs as many
buffer registers as desired and then issues an I/O update. The
I/O update occurs by writing to Register 0005, Bit 0 = 1 (or by
the external application of the necessary logic level to one of the
multifunction pins previously programmed as an I/O update
input). The contents of buffer registers connected directly to the
internal device functions affect those functions immediately.
The contents of buffer registers that connect to active registers
do not affect the internal device functions until the I/O update
event occurs.
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An S or C in the Opt column of the register map identifies a
register as an active register (otherwise, it is a buffer register).
An S entry means that the I/O update signal to the active register is
synchronized with the serial port clock or with an input signal
driving one of the multifunction pins. On the other hand, a C
entry means that the I/O update signal to the active register is
synchronized with a clock signal derived from the internal
system clock (f
When reading back a register that has both buffered and active
contents, the user can use Register 0004, Bit 0 to select whether
to read back the buffer or active contents. Readback of the
active contents occurs when Register 0004, Bit 0 = 0, whereas
readback of the buffer contents occurs when Register 0004,
Bit 0 = 1. Note that a read-only active register requires an
I/O update before reading its contents.
AUTOCLEAR REGISTERS
An A in the Opt column of the register map identifies an auto-
clear register. Typically, the active value for an autoclear register
takes effect following an I/O update. The bit is cleared by the
internal device logic upon completion of the prescribed action.
SCLK/SCL
CS/SDA
SDIO
SDO
MULTIFUNCTION
5
3
4
2
S
/32), as shown in Figure 65.
CONTROL
Figure 65. Buffered and Active Registers
PIN LOGIC
SERIAL
PORT
FROM
DETECT
EDGE
f
S
/32