AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 107

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CALCULATING DIGITAL FILTER COEFFICIENTS
The digital loop filter coefficients ( , , , and (see Figure 40))
relate to the time constants (T
equivalent analog circuit for a third order loop filter (Figure 66).
The design process begins by deciding on two design
parameters related to the second order loop filter shown in
Figure 67: the desired open-loop bandwidth (f
margin ( .
An analysis of the second order loop filter leads to its primary
time constant, T
of f
where
An analysis of the third order loop filter leads to the definition
of another time constant, T
expressible in terms of the desired amount of additional
attenuation introduced by R
frequency offset (f
where
Note that ATTEN is the desired excess attenuation in decibels.
Furthermore, ATTEN and ω
With an expression for T
adjusted open-loop bandwidth (f
can be shown that ω
expressible in terms of T
P
and as
T
T
T
1
3
3
OFFSET
P
1
5
10
P
CHARGE
1
f
2
cos(
P
sin(
Figure 67. Second Order Analog Loop Filter
FROM
PUMP
ATTEN
OFFSET
Figure 66. Third Order Analog Loop Filter
f
10
1
CHARGE
. It can be shown that T
P
OFFSET
2
FROM
PUMP
.
)
)
C
f
1
OFFSET
(f
) from the PLL output frequency.
C
1
1
expressed as a radian frequency) is
, T
and T
C1
3
. It can be shown that T
3
3
OFFSET
, and θ (phase margin) as
.
and C
1
C1
, T
3
, it is possible to define an
C
2
) that is slightly less than f
, and T
should be chosen so that
C2
3
R3
at some specified
C3
C2
1
3
) associated with the
is expressible in terms
TO
VCO
P
) and phase
TO
VCO
3
is
Rev. A | Page 107 of 112
P
. It
It can also be shown that the adjusted open-loop bandwidth
leads to T
loop filter) expressed as
Calculation of the digital loop filter coefficients requires a
scaling constant, K (related to the system clock frequency, f
and the PLL feedback divide ratio, D.
where S, U, and V are the integer and fractional feedback
divider values that reside in the profile registers. Keep in mind
that the desired integer feedback divide ratio is one more than
the stored value of S (hence, the +1 term in the equation for D
in this equation). This leads to the digital filter coefficients
given by
Calculation of the coefficient register values requires the
application of some special functions described as follows:
The if() function
where test_statement is a conditional expression (for example, x
< 3), true_value is what y equals if the conditional expression is
true, and false_value is what y equals if the conditional
expression is false.
The round() function
y = if(test_statement, true_value, false_value)
y = round(x)
T
K
D
2
C
S
f
2
f
30
32
S
S
f
T
(the secondary time constant of the second order
32
C
32
T
T
T
S
1
,
T
517
2
1
1
T
3
U
V
T
1
C
K
⎛
⎜ ⎜
⎝
3
2
2
2
T
D
1
,
33
T
578
1
T
1
3
T
1
1
1
tan(
,
125
1
T
1
2
T
T
⎞
⎟ ⎟
⎠
3
3
f
)
S
2
C
1
⎡
⎢
⎢
⎣
T
1
1
2
C
1
T
T
T
1
2
T
1
3
2
T
C
T
3
T
3
1
tan(
2
T
3
)
2
2
AD9548
1
⎤
⎥
⎥
⎦
S
),