AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 57

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Transfer Format
Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
Send byte format—the send byte protocol is used to set up the register address for subsequent reads.
Receive byte format—the receive byte protocol is used to read the data byte(s) from RAM starting from the current address.
Read byte format—the combined format of the send byte and the receive byte.
I²C Serial Port Timing
Table 34. I2C Timing Definitions
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
S
S
SCL
S
BUF
HD; STA
SU; STA
SU; STO
HD; DAT
SU; DAT
LO
HI
R
F
SP
S
Address
Slave
address
SDA
SCL
Slave
Slave address
t
Slave address
F
S
W
W
t
HD; STA
A
Description
Serial clock
Bus free time between stop and start conditions
Repeated hold time start condition
Repeated start condition setup time
Stop condition setup time
Data hold time
Date setup time
SCL clock low period
SCL clock high period
Minimum/maximum receive SCL and SDA rise time
Minimum/maximum receive SCL and SDA fall time
Pulse width of voltage spikes that must be suppressed by the input filter
t
LO
A
High Byte
Address
RAM
W
RAM address
t
R
R
high byte
t
HD; DAT
A
A
t
A
SU; DAT
Low Byte
Address
t
HI
RAM Data 0
RAM
RAM address high byte
A
t
F
Figure 64. I²C Serial Port Timing
RAM address
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A
low byte
t
SU; STA
Sr
A
Address
Sr
Slave
A
RAM Data 1
t
HD; STA
Data 0
A
R
RAM
A
RAM
Data
A
t
RAM address low byte
0
SP
t
SU; STO
A
Data 1
RAM
A
t
R
RAM Data 2
RAM
Data
1
P
A
t
BUF
A
Data 2
RAM
S
RAM
Data
2
AD9548
A
A
A
A
P
P
P
P