AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 25

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Program the Clock Distribution Outputs
The clock distribution parameters reside in the 0400 register
address space. They include the following:
Program the Reference Inputs
The reference input parameters reside in the 0500 register
address space. They include the following:
Program the Reference Profiles
The reference profile parameters reside in the 0600 to 0700
register address space. They include the following:
Output power-down control
Output enable (disabled by default)
Output synchronization
Output mode control
Output divider functionality
Reference power-down
Reference logic family
Reference profile assignment control
Phase build-out control
Reference priority
Reference period
Reference period tolerance
Reference validation timer
Reference redetect timer
Digital loop-filter coefficients
Reference prescaler (R-divider)
Feedback dividers (S, U, and V)
Phase and frequency lock detector controls
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Generate the Reference Acquisition
After the registers are programmed, issue an I/O update using
Register 0005, Bit 0 to invoke all of the register settings
programmed up to this point.
If the settings are programmed for manual profile assignment,
the DPLL locks to the first available reference that has the
highest priority. If the settings are programmed for automatic
profile assignment, then write to the reference profile detect
register (Address 0A0D) to select the state machines that
require starting. Next, issue an I/O update (Address 0005, Bit 0)
to start the selected state machines. Upon completion of the
reference detection sequence, the DPLL locks to the first
available reference with the highest priority.
Generate the Output Clock
If the registers are programmed for automatic clock distribution
synchronization via DPLL phase or frequency lock, the syn-
thesized output signal appears at the clock distribution outputs
(assuming the output is enabled and that the DDS output signal
has been routed to the CLKIN input pins). Otherwise, set and
then clear the sync distribution bit (Address 0A02, Bit 1) or use
a multifunction pin input (if programmed accordingly) to generate
a clock distribution sync pulse, which causes the synthesized
output signal to appear at the clock distribution outputs.
AD9548