AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 38

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
The LF path permits the user to provide an LVPECL, LVDS,
CMOS, or sinusoidal low frequency clock for multiplication by
the integrated SYSCLK PLL. The LF path handles input
frequencies from 3.5 MHz up to 100 MHz. However, when
using a sinusoidal input signal, it is best to use a frequency in
excess of 20 MHz. Otherwise, the resulting low slew rate can
lead to substandard noise performance. Note that the LF path
includes an optional 2× frequency multiplier to double the rate
at the input to the SYSCLK PLL and potentially reduce the PLL
in-band noise. However, to avoid exceeding the maximum PFD
rate of 150 MHz, using the 2× frequency multiplier is valid only
for input frequencies below 125 MHz.
The XTAL path enables the connection of a crystal resonator
(typically 10 MHz to 50 MHz) across the SYSCLKx input pins.
An internal amplifier provides the negative resistance required
to induce oscillation. The internal amplifier expects a 3.2 mm ×
2.5 mm AT cut, fundamental mode crystal with a maximum
motional resistance of 100 Ω. The following crystals, listed in
alphabetical order, may meet these criteria. Note that, whereas
these crystals may meet the preceding criteria according to their
data sheets, Analog Devices, Inc., does not guarantee their
operation with the AD9548 nor does Analog Devices endorse
one crystal manufacturer/supplier over another.
SYSCLK PLL MULTIPLIER
The SYSCLK PLL multiplier is an integer-N design and relies on
an integrated LC tank and VCO. It provides a means to convert
a low frequency clock input to the desired system clock
frequency, f
accepts input signals between 3.5 MHz and 500 MHz, but
frequencies in excess of 150 MHz require the M-divider to
ensure compliance with the maximum PFD rate (150 MHz).
The PLL contains a feedback divider (N) that is programmable
for divide values between 6 and 255. The nominal VCO gain is
70 MHz/V.
Lock Detector
The SYSCLK PLL has a built-in lock detector. Register 0100,
Bit 2 determines whether the lock detector is active. When
active (default), the user controls the sensitivity of the lock
detector via the lock detect divider bits (Register 0100, Bits[1:0]).
AVX/Kyocera CX3225SB
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Siward SX-3225
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(900 MHz to 1 GHz). The SYSCLK PLL multiplier
Rev. A | Page 38 of 112
Note that 0 must be written to the system clock stability timer
(Register 0106 to Register 0108) whenever the lock detector is
disabled (Register 0100, Bit 2 = 1).
The SYSCLK PLL phase detector operates at the PFD rate,
which is f
reference and feedback signals are phase aligned (within a
certain threshold range).
While the PLL is in the process of acquiring a lock condition,
the PFD samples typically consist of an arbitrary sequence of
complete phase lock, the number of consecutive in-phase PFD
samples grows larger. Thus, one way of indicating a locked
condition is to count the number of consecutive in-phase PFD
samples and if it exceeds a certain value, then declare the PLL
locked.
This is exactly the role of the lock detect divider bits. When the
lock detector is enabled (Register 0100, Bit 2 = 0), the lock detect
divider bits determine the number of consecutive in-phase
decisions required (128, 256, 512, or 1024) before the lock
detector declares a locked condition. The default setting is 128.
Charge Pump
The charge pump operates in either automatic or manual mode
based on the charge pump mode bit (Register 0100, Bit 6).
When Register 0100, Bit 6 = 0, the AD9548 automatically
selects the appropriate charge pump current based on the
N-divider value. Note that the user cannot control the charge
pump current bits (Register 0100, Bits[5:3]) in automatic mode.
When Register 0100, Bit 6 = 1, the user determines the charge
pump current via the charge pump current bits (Register 0100,
Bits[5:3]). The charge pump current varies from 125 μA to 1
mA in 125 μA steps. The default setting is 500 μA.
SYSCLK PLL Loop Filter
The AD9548 has an internal second order loop filter that estab-
lishes the loop dynamics for input signals between 12.5 MHz
and 100 MHz. By default, the device uses the internal loop filter.
However, an external loop filter option is available by setting the
external loop filter enable bit (Register 0100, Bit 7). This
bypasses the internal loop filter and allows the device to use an
externally connected second order loop filter, as shown in
Figure 46.
in-phase and out-of-phase indications. As the PLL approaches
VCO
/N. Each PFD sample indicates whether the
Figure 46. External Loop Filter Schematic
SYSCLK_VREG
48
AD9548
R1
C2
SYSCLK_LF
C1
49