AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 18

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
TYPICAL PERFORMANCE CHARACTERISTICS
f
loop bandwidth; PLL off = SYSCLK PLL bypassed; PLL on = SYSCLK PLL enabled; I
PLL loop filter. AVDD, AVDD3, and DVDD at nominal supply voltage, f
R
= input reference clock frequency; f
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
–70
–80
–90
–70
–80
–90
100
100
Figure 3. Additive Phase Noise (Output Driver = LVPECL),
Figure 4. Additive Phase Noise (Output Driver = LVPECL),
LBW = 1 kHz, f
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 173fs (–75.4dBc)
20kHz TO 80MHz: 315fs (–70.2dBc) (EXTRAPOLATED)
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 333fs (–69.8dBc)
20kHz TO 80MHz: 430fs (–67.6dBc) (EXTRAPOLATED)
1k
1k
LBW = 1 kHz, f
f
f
R
R
= 19.44 MHz, f
= 19.44 MHz, f
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
10k
10k
SYS
= 50 MHz (Crystal), PLL On
SYS
100k
100k
O
O
= 1 GHz, PLL Off
= 155.52 MHz,
= 155.52 MHz,
O
= clock frequency; f
1M
1M
10M
10M
100M
100M
SYS
= SYSCLK input frequency; f
Rev. A | Page 18 of 112
S
= 1 GHz, I
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
–70
–80
–90
–70
–80
–90
CP
100
100
Figure 5. Additive Phase Noise (Output Driver = LVPECL),
Figure 6. Additive Phase Noise (Output Driver = LVPECL),
CP
= automatic mode, LF = internal, unless otherwise noted.
= SYSCLK PLL charge pump current; LF = SYSCLK
S
= internal system clock frequency; LBW = DPLL
LBW = 1 kHz, f
1k
1k
LBW = 1 kHz, f
f
f
R
R
= 19.44 MHz, f
= 19.44 MHz, f
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 310fs (–64.4dBc)
20kHz TO 80MHz: 330fs (–63.9dBc)
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 103fs (–74.0dBc)
20kHz TO 80MHz: 160fs (–70.1dBc)
10k
10k
SYS
= 50 MHz (Crystal), PLL On
SYS
100k
100k
O
= 1 GHz, PLL Off
O
= 311.04 MHz,
= 311.04 MHz,
1M
1M
10M
10M
100M
100M