AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 45

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bits[6:0]
Value
16
17
18
19
20
21 to 31
32
33
34
35
36
37
38
39
40 to 47
48
49
50
51
52
53
54
55
56 to 63
64
65
66
67
68
69
70 to 127
Output Function
Holdover
Free run
Reset incremental phase
offset
Increment incremental
phase offset
Decrement incremental
phase offset
Unused
Override Reference
Monitor A
Override Reference
Monitor AA
Override Reference
Monitor B
Override Reference
Monitor BB
Override Reference
Monitor C
Override Reference
Monitor CC
Override Reference
Monitor D
Override Reference
Monitor DD
Unused
Force validation
Timeout A
Force validation
Timeout AA
Force validation
Timeout B
Force validation
Timeout BB
Force validation
Timeout C
Force validation
Timeout CC
Force validation
Timeout D
Force validation
Timeout DD
Unused
Enable OUT0
Enable OUT1
Enable OUT2
Enable OUT3
Enable OUT0, OUT1,
OUT2, OUT3
Sync clock distribution
outputs
Unused
Destination Proxy
Register 0A01, Bit 6
Register 0A01, Bit 5
Register 0A0C, Bit 2
Register 0A0C, Bit 0
Register 0A0C, Bit 1
Register 0A0F, Bit 0
Register 0A0F, Bit 1
Register 0A0F, Bit 2
Register 0A0F, Bit 3
Register 0A0F, Bit 4
Register 0A0F, Bit 5
Register 0A0F, Bit 6
Register 0A0F, Bit 7
Register 0A0E, Bit 0
Register 0A0E, Bit 1
Register 0A0E, Bit 2
Register 0A0E, Bit 3
Register 0A0E, Bit 4
Register 0A0E, Bit 5
Register 0A0E, Bit 6
Register 0A0E, Bit 7
Register 0401, Bit 0
Register 0401, Bit 1
Register 0401, Bit 2
Register 0401, Bit 3
Register 0401,
Bits[3:0]
Register 0A02, Bit 1
Rev. A | Page 45 of 112
If more than one multifunction pin operates on the same
control signal, then internal priority logic ensures that only one
multifunction pin serves as the signal source. The selected pin is
the one with the lowest numeric suffix. For example, if both M3
and M7 operate on the same control signal, then M3 is used as
the signal source and the redundant pins are ignored.
At power-up, the multifunction pins can be used to force the
device into certain configurations as defined in the initial pin
programming section. This functionality, however, is valid only
during power-up or following a reset, after which the pins can
be reconfigured via the serial programming port or via the
EEPROM.
IRQ PIN
The AD9548 has a dedicated interrupt request (IRQ) pin. The
IRQ pin output mode register (Register 0208, Bits[1:0]) controls
how the IRQ pin asserts an interrupt based on the value of the
two bits, as follows:
00—The IRQ pin is high impedance when deasserted and active
01—The IRQ pin is high impedance when deasserted and active
10—The IRQ pin is Logic 0 when deasserted and Logic 1 when
11—The IRQ pin is Logic 1 when deasserted and Logic 0 when
The AD9548 asserts the IRQ pin whenever any of the bits in the
IRQ monitor register (Address 0D02 to Address 0D09) are
Logic 1. Each bit in this register is associated with an internal
function capable of producing an interrupt. Furthermore, each
bit of the IRQ monitor register is the result of a logical AND of
the associated internal interrupt signal and the corresponding
bit in the IRQ mask register (Address 0209 to Address 0210).
That is, the bits in the IRQ mask register have a one-to-one
correspondence with the bits in the IRQ monitor register.
Whenever an internal function produces an interrupt signal
and the associated IRQ mask bit is set, then the corresponding
bit in the IRQ monitor register is set. The user should be aware
that clearing a bit in the IRQ mask register removes only the
mask associated with the internal interrupt signal. It does not
clear the corresponding bit in the IRQ monitor register.
The IRQ pin is the result of a logical OR of all the IRQ monitor
register bits. Thus, the AD9548 asserts the IRQ pin so long as
any of the IRQ monitor register bits are Logic 1. Note that it is
possible to have multiple bits set in the IRQ monitor register.
Therefore, when the AD9548 asserts the IRQ pin, it may
indicate an interrupt from several different internal functions.
The IRQ monitor register provides the user with a means to
interrogate the AD9548 to determine which internal function(s)
produced the interrupt.
low when asserted and requires an external pull-up resistor
(this is the default operating mode).
high when asserted and requires an external pull-down
resistor.
asserted.
asserted.
AD9548