AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 4

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for AVDD3 = DVDD_I/O = 3.3 V; AVDD = DVDD = 1.8 V; T
SUPPLY VOLTAGE
Table 1.
Parameter
SUPPLY VOLTAGE
SUPPLY CURRENT
The test conditions for the maximum (max) supply current are the same as the test conditions for the All Blocks Running parameter of Table 3.
The test conditions for the typical (typ) supply current are the same as the test conditions for the Typical Configuration parameter of Table 3.
Table 2.
Parameter
SUPPLY CURRENT
POWER DISSIPATION
Table 3.
Parameter
POWER DISSIPATION
DVDD3
DVDD
AVDD3
AVDD
I
I
I
I
I
Typical Configuration
All Blocks Running
Full Power-Down
DVDD3
DVDD
AVDD3
AVDD3
AVDD
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
Min
3.135
1.71
3.135
3.135
1.71
1.71
Min
Min
Typ
3.30
1.80
3.30
3.30
1.80
1.80
Typ
1.5
190
52
24
24
135
Typ
800
900
13
Rev. A | Page 4 of 112
Max
3.465
1.89
3.465
3.465
1.89
1.89
Max
3
215
75
110
110
163
Max
1100
1400
Unit
V
V
V
Unit
mA
mA
mA
mA
mA
mA
Unit
mW
mW
mW
V
V
V
A
= 25°C; I
Test Conditions/Comments
Pin 7, Pin 82
Pin 1, Pin 6, Pin 12, Pin 14, Pin 15, Pin 77, Pin 83, Pin 88
Pin 21, Pin 22, Pin 47, Pin 60, Pin 66, Pin 67, Pin 73
Pin 31, Pin 37, Pin 38, Pin 44
Pin 31, Pin 37, Pin 38, Pin 44
Pin 23, Pin 24, Pin 29, Pin 34, Pin 41, Pin 50, Pin 55, Pin 59,
Pin 63, Pin 70, Pin 74
Test Conditions/Comments
Pin 7, Pin 82
Pin 1, Pin 6, Pin 12, Pin 14, Pin 15, Pin 77, Pin 83, Pin 88
Pin 21, Pin 22, Pin 47, Pin 60, Pin 66, Pin 67, Pin 73
Pin 31, Pin 37, Pin 38, Pin 44
Pin 31, Pin 37, Pin 38, Pin 44
Pin 23, Pin 24, Pin 29, Pin 34, Pin 41, Pin 50, Pin 55, Pin 59,
Pin 63, Pin 70, Pin 74
Test Conditions/Comments
f
LVPECL clock distribution output running at 122.88 MHz
(all others powered down); one input reference running
at 100 MHz (all others powered down)
f
distribution outputs configured as LVPECL at 399 MHz; all
input references configured as differential at 100 MHz;
fractional-N active (R = 10, S = 39, U = 9, V = 10)
Conditions = typical configuration; no external pull-up or
pull-down resistors
SYSCLK
SYSCLK
DAC
= 20 MHz
= 20 MHz
= 20 mA (full scale), unless otherwise noted.
1
1
; f
; f
S
S
= 1 GHz
= 1 GHz
2
2
; f
; f
DDS
DDS
= 399 MHz
= 122.88 MHz
3
; all clock
3
; one