AD9548/PCBZ Analog Devices Inc, AD9548/PCBZ Datasheet - Page 76

• Manufacturer Part Number: AD9548/PCBZ
• Description: Clock Generator Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9548/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9548
• Kit Contents: Board
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9548
• Primary Attributes: 62.5 ~ 450 MHz Output Frequency
• Secondary Attributes: SPI and I2C Compatible Control Port
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
Table 61. Incremental Closed-Loop Phase Lock Offset Step Size
Address
0314
0315
1
Table 62. Phase Slew Rate Limit
Address
0316
0317
1
Table 63. History Accumulation Timer
Address
0318
0319
031A
1
Table 64. History Mode
Address
031B
The default incremental closed-loop phase lock offset step size value is 0x03E8 = 1000 (1 ns).
The default phase slew rate limit is 0 (or disabled).
Do not program a timer value of 0. The history accumulation timer default value is 0x007530 = 30,000 (30 sec).
Bits
[7:0]
[7:0]
Bits
[7:0]
[7:0]
Bits
[7:0]
[7:0]
[7:0]
Bits
[7:5]
[4]
[3]
[2:0]
Bit Name
Incremental phase
lock offset step size
(expressed in pico-
seconds per step)
Bit Name
Phase slew limit
(expressed in nano-
seconds per second)
Bit Name
History accumulation
timer (expressed in
milliseconds)
Bit Name
Unused
Single-sample fallback
Persistent history
Incremental average
1
1
Description
Phase slew rate limit, Bits[7:0]
Phase slew rate limit, Bits[15:8]
Description
History accumulation timer, Bits[7:0]
History accumulation timer, Bits[15:8]
History accumulation timer, Bits[23:16]
Description
Incremental phase lock offset step size, Bits[7:0]
Incremental phase lock offset step size, Bits[15:8]
Description
Controls the holdover history. If tuning word history is not available for the
reference that was active just prior to holdover, then
0 (default) = use the free running frequency tuning word register value.
1 = use the last tuning word from the DPLL.
Controls the holdover history initialization. When switching to a new reference
0 (default) = clear the tuning word history.
1 = retain the previous tuning word history.
History mode value from 0 to 7 (default = 0).
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