MCU, MPU & DSP Development Tools LatticeECP3 PCI Express Dev Kit

LFE3-95E-PCIE-DKN

Manufacturer Part NumberLFE3-95E-PCIE-DKN
DescriptionMCU, MPU & DSP Development Tools LatticeECP3 PCI Express Dev Kit
ManufacturerLattice
LFE3-95E-PCIE-DKN datasheet
 

Specifications of LFE3-95E-PCIE-DKN

Processor To Be EvaluatedLFE3-95EA-xProcessor SeriesLatticeECP3
Interface TypeSPIOperating Supply Voltage1.2 V to 3.3 V
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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LatticeECP3 Family Data Sheet
Preliminary DS1021 Version 01.6, March 2010

LFE3-95E-PCIE-DKN Summary of contents

  • Page 1

    ... LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010 ...

  • Page 2

    ... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 3

    ... The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to 486 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel I/O standards. ...

  • Page 4

    ... The LatticeECP3 devices use 1.2V as their core voltage. © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 5

    ... Note: There is no Bank 4 or Bank 5 in LatticeECP3 devices. PFU Blocks The core of the LatticeECP3 device consists of PFU blocks, which are provided in two forms, the PFU and PFF. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions ...

  • Page 6

    ... LUT4 & CARRY CARRY CARRY Slice 1 Slice Routing PFU BLock Modes Logic, ROM 2-3 Architecture LatticeECP3 Family Data Sheet LUT4 & LUT4 LUT4 CARRY Slice PFF Block Resources Modes Logic, Ripple, ROM Logic, Ripple, ROM Logic, Ripple, ROM 2 LUT4s Logic, ROM ...

  • Page 7

    ... F0, F1 LUT4 output register bypass signals Q0, Q1 Register outputs OFX0 Output of a LUT5 MUX OFX1 Output of a LUT6, LUT7, LUT8 FCO Slice 2 of each PFU is the fast carry chain output 2-4 LatticeECP3 Family Data Sheet SLICE OFX1 FF* To Routing LUT5 Mux ...

  • Page 8

    ... LatticeECP3 devices support distributed memory initialization. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives ...

  • Page 9

    ... PFU configuration. For more information, please refer to TN1179, Routing There are many resources provided in the LatticeECP3 devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. ...

  • Page 10

    ... Dynamic coarse phase shift, falling edge setting Delay Locked Loops (DLL) In addition to PLLs, the LatticeECP3 family of devices has two DLLs per device. CLKI is the input frequency (generated either from the pin or routing) for the DLL. CLKI feeds into the output muxes block to bypass the DLL, directly to the DELAY CHAIN block and (directly or through divider circuit) to the reference input of the Phase Detector (PD) input mux ...

  • Page 11

    ... DLL inputs and outputs. The user can configure the DLL for many common functions such as time reference delay mode and clock injection removal mode. Lattice provides primitives in its design tools for these functions. Figure 2-5. Delay Locked Loop Diagram (DLL) ALUHOLD ÷ ...

  • Page 12

    ... Gray-coded digital control bus to other DLLs via CIB LatticeECP3 devices have two general DLLs and four Slave Delay lines, two per DLL. The DLLs are in the lowest EBR row and located adjacent to the EBR. Each DLL replaces one EBR block. One Slave Delay line is placed adja- cent to the DLL and the duplicate Slave Delay line (in Figure 2-6) for the DLL is placed in the I/O ring between Banks 6 and 7 and Banks 2 and 3 ...

  • Page 13

    ... Figure 2-7. Sharing of PIO Pins by PLLs and DLLs in LatticeECP3 Devices Clock Dividers LatticeECP3 devices have two clock dividers, one on the left side and one on the right side of the device. These are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or ÷ ...

  • Page 14

    ... LatticeECP3 devices derive clocks from six primary source types: PLL outputs, DLL outputs, CLKDIV outputs, ded- icated clock inputs, routing and SERDES Quads. LatticeECP3 devices have two to ten sysCLOCK PLLs and two DLLs, located on the left and right sides of the device. There are six dedicated clock inputs: two on the top side, two on the left side and two on the right side of the device ...

  • Page 15

    ... Lattice Semiconductor Figure 2-10. Primary Clock Sources for LatticeECP3-35 PLL Input Clock Input Clock Input DLL Input PLL Input Figure 2-11. Primary Clock Sources for LatticeECP3-70, -95, -150 PLL Input PLL Input Clock Input Clock Input DLL Input PLL Input PLL Input ...

  • Page 16

    ... A global primary clock is a primary clock that is distributed to all quadrants. The clock routing structure in LatticeECP3 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The pri- mary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources are connected to these muxes ...

  • Page 17

    ... This special vertical routing channel aligns with either the left edge of the center DSP slice in the DSP row or the center of the DSP row. Figure 2-15 shows this special vertical routing channel and the 20 secondary clock regions for the LatticeECP3 family of devices. All devices in the LatticeECP3 family have eight Clock ...

  • Page 18

    ... Lattice Semiconductor secondary clock resources per region (SC0 to SC7). The same secondary clock routing can be used for control signals. Table 2-6. Secondary Clock Regions Figure 2-15. LatticeECP3-70 and LatticeECP3-95 Secondary Clock Regions sysIO Bank 0 Secondary Clock Region R1C1 Secondary Clock Region R2C1 ...

  • Page 19

    ... Secondary Clock Feedlines: 8 PIOs + 16 Routing 8:1 8:1 8:1 8:1 SC2 SC3 SC4 SC5 8 Secondary Clocks (SC0 to SC7) per Region Clock/Control Primary Clock 8 7 28:1 Routing 12 Vcc 1 5 Routing 20:1 14 Vcc 1 2-16 Architecture LatticeECP3 Family Data Sheet 8:1 8:1 SC6 SC7 Clock to Slice Slice Control ...

  • Page 20

    ... The top left and top right PLL can also drive the two top edge clocks. Edge Clock Routing LatticeECP3 devices have a number of high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. There are six edge clocks per device: two edge clocks on each of the top, left, and right edges ...

  • Page 21

    ... Routing CLKINDEL (Left DLL_DEL) Input Pad Top Right PLL_CLKOP Top Left PLL_CLKOS 7:1 Right DLL_CLKOP Left DLL_CLKOS Routing CLKINDEL (Right DLL_DEL) 2-18 Architecture LatticeECP3 Family Data Sheet Left and Right Edge Clocks ECLK1 Left and Right Edge Clocks ECLK2 ECLK1 ECLK2 ...

  • Page 22

    ... ROM. Memory Cascading Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. LatticeECP3 Memory Usage ...

  • Page 23

    ... Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds. The LatticeECP3, on the other hand, has many DSP slices that support different data widths. Memory Core ...

  • Page 24

    ... General Purpose DSP LatticeECP3 sysDSP Slice Architecture Features The LatticeECP3 sysDSP Slice has been significantly enhanced to provide functions needed for advanced pro- cessing applications. These enhancements provide improved flexibility and resource utilization. The LatticeECP3 sysDSP Slice supports many functions that include the following: • ...

  • Page 25

    ... For most cases, as shown in Figure 2-24, the LatticeECP3 DSP slice is backwards-compatible with the LatticeECP2™ sysDSP block, such that, legacy applications can be targeted to the LatticeECP3 sysDSP slice. The functionality of one LatticeECP2 sysDSP Block can be mapped into two adjacent LatticeECP3 sysDSP slices, as shown in Figure 2-25. ...

  • Page 26

    ... The LatticeECP2 sysDSP block supports the following basic elements. • MULT (Multiply) • MAC (Multiply, Accumulate) • MULTADDSUB (Multiply, Addition/Subtraction) • MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation) Table 2-8 shows the capabilities of each of the LatticeECP3 slices versus the above functions. Table 2-8. Maximum Number of Elements in a Slice Width of Multiply MULT MAC ...

  • Page 27

    ... PR = Pipeline Register OR = Output Register FR = Flag Register LatticeECP3 sysDSP Usage From FPGA Core AA AB OPCODE IR IR MULTA A_ALU 0 AMUX R= A ± B ± Logic ( FPGA Core 2-24 Architecture LatticeECP3 Family Data Sheet Guide SROB SROA MULTB PR B_ALU 0 Next DSP Slice BMUX COUT ALU = = FR OR ...

  • Page 28

    ... The output register is used to store the accumulated value. The ALU is con- figured as the accumulator in the sysDSP slice in the LatticeECP3 family can be initialized dynamically. A regis- tered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-27 shows the MAC sysDSP element ...

  • Page 29

    ... Lattice Semiconductor MMAC DSP Element The LatticeECP3 supports a MAC with two multipliers. This is called Multiply Multiply Accumulate or MMAC. In this case, the two operands, AA and AB, are multiplied and the result is added with the previous accumulated value and with the result of the multiplier operation of operands BA and BB. This accumulated value is available at the output. ...

  • Page 30

    ... IR = Input Register PR = Pipeline Register OR = Output Register FR = Flag Register From FPGA Core AA AB OPCODE IR IR MULTA A_ALU 0 AMUX R= A ± B ± Logic ( FPGA Core 2-27 Architecture LatticeECP3 Family Data Sheet BA BB SROB SROA MULTB PR B_ALU 0 Next DSP Slice BMUX COUT ALU = = FR OR ...

  • Page 31

    ... IR = Input Register PR = Pipeline Register OR = Output Register FR = Flag Register From FPGA Core AA AB OPCODE MULTA A_ALU B_ALU 0 0 AMUX BMUX R= A ± B ± Logic ( FPGA Core 2-28 Architecture LatticeECP3 Family Data Sheet BA BB SROB IR IR SROA MULTB PR Next DSP Slice COUT ALU OR ...

  • Page 32

    ... DSP slices, improving the performance. Cascading of slices uses the signals CIN, COUT and C Mux of the slice. Addition The LatticeECP3 sysDSP slice allows for the bypassing of multipliers and cascading of adder logic. High perfor- mance adder functions are implemented without the use of LUTs. The maximum width adders that can be imple- mented are 54-bit ...

  • Page 33

    ... Resources Available in the LatticeECP3 Family Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP3 family. Table 2-10 shows the maximum available EBR RAM Blocks in each LatticeECP3 device. EBR blocks, together with Distributed RAM can be used to store variables locally for fast DSP operations. ...

  • Page 34

    ... Control Muxes CLK CEOT LSR GSR CEI PIOB DQS Control Block (One per DQS Group of 12 I/Os)*** Read Control DDRLAT* DDRCLKPOL* ECLKDQSR* Write Control DQCLK0* DQCLK1* DQSW* 2-31 Architecture LatticeECP3 Family Data Sheet PADA “T” sysIO Buffer PADB “C” ...

  • Page 35

    ... Status flag from DATAVALID logic, used to indicate when input data is captured in IOLOGIC and valid to core. Read signal for DDR memory interface Unshifted DQS strobe from input pad DQSI biased to go high when DQSI is tristate, goes to input logic block as well as core logic. 2-32 Architecture LatticeECP3 Family Data Sheet ...

  • Page 36

    ... Figure 2-37 for an overview of the DQS read control logic. Further discussion about using the DQS strobe in this module is discussed in the DDR Memory section of this data sheet. Please see TN1180, LatticeECP3 High-Speed I/O Interface LatticeECP3 Family Data Sheet for more information on this topic. 2-33 Architecture ...

  • Page 37

    ... Further discussion on using the DQS strobe in this module is discussed in the DDR Memory section of this data sheet. DDR Registers Synch Registers CLKP for more information on this topic. 2-34 Architecture LatticeECP3 Family Data Sheet Clock Transfer & Gearing Registers* DDRLAT Config bit INB IPB ...

  • Page 38

    ... This block is controlled by a 3-bit delay control that can be set in the DQS control logic block. For more information about this topic, please see the list of technical documentation at the end of this data sheet DDR Gearing & ISI Correction Config Bit 2-35 Architecture LatticeECP3 Family Data Sheet Tristate Logic TO Output Logic DO ISI ...

  • Page 39

    ... DLL Calibrated DQS Delay Block Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. For most interfaces, a PLL is used for this adjustment. However, in DDR memories the clock LatticeECP3 Family Data Sheet PADA "T" PIO A LVDS Pair PADB " ...

  • Page 40

    ... DQS output in the DQS output register block. Figure 2-36 and Figure 2-37 show how the DQS transition signals that are routed to the PIOs. Please see TN1180, LatticeECP3 High-Speed I/O Interface LatticeECP3 Family Data Sheet for more information on this topic. 2-37 Architecture ...

  • Page 41

    ... DQS Strobe and Transition Detect Logic I/O Ring *Includes shared configuration I/Os and dedicated configuration I/Os. Bank 1 DQS DQS DQS DQS DQS DDR DLL (Right) SERDES 2-38 Architecture LatticeECP3 Family Data Sheet Configuration Bank DQS Delay Control Bus ECLK1 ECLK2 DQCLK0 DQCLK1 DDRLAT DDRCLKPOL ECLKDQSR DATAVALID ...

  • Page 42

    ... In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. The LatticeECP3 family contains dedicated circuits to transfer data between these domains. A clock polarity selector is used to prevent set-up and hold violations at the domain transfer between DQS (delayed) and the system clock ...

  • Page 43

    ... LVPECL, PCI. sysI/O Buffer Banks LatticeECP3 devices have six sysI/O buffer banks: six banks for user I/Os arranged two per side. The banks on the bottom side are wraparounds of the banks on the lower right and left sides. The seventh sysI/O buffer bank (Config- uration Bank) is located adjacent to Bank 2 and has dedicated/shared I/Os for configuration ...

  • Page 44

    ... V REF2(6) V CCIO6 GND LatticeECP3 devices contain two types of sysI/O buffer pairs. 1. Top (Bank 0 and Bank 1) and Bottom sysI/O Buffer Pairs (Single-Ended Outputs Only) The sysI/O buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con- figured as a differential input. Only the top edge buffers have a programmable PCI clamp. ...

  • Page 45

    ... CCIO all the I/O banks that are critical to the application. For more information about controlling the output logic state with valid input logic levels during power-up in LatticeECP3 devices, see the list of technical documentation at the end of this data sheet. The V ...

  • Page 46

    ... Lattice Semiconductor On-Chip Programmable Termination The LatticeECP3 supports a variety of programmable on-chip terminations options, including: • Dynamically switchable Single Ended Termination for SSTL15 inputs with programmable resistor values of 40, 50 ohms. This is particularly useful for low power JEDEC compliant DDR3 memory controller imple- mentations. External termination to Vtt should be used for DDR2 memory controller implementation. • ...

  • Page 47

    ... LatticeECP3 devices feature channels of embedded SERDES/PCS arranged in quads at the bottom of the devices supporting up to 3.2Gbps data rate. Figure 2-40 shows the position of the quad blocks for the LatticeECP3- 150 devices. Table 2-14 shows the location of available SERDES Quads for all devices. ...

  • Page 48

    ... Lattice Semiconductor Figure 2-40. SERDES/PCS Quads (LatticeECP3-150) Table 2-13. LatticeECP3 SERDES Standard Support Standard PCI Express 1.1 Gigabit Ethernet SGMII XAUI Serial RapidIO Type I, Serial RapidIO Type II, Serial RapidIO Type III CPRI-1, CPRI-2, CPRI-3, CPRI-4 SD-SDI (259M, 344M) HD-SDI (292M) 3G-SDI ...

  • Page 49

    ... Lattice Semiconductor Table 2-14. Available SERDES Quads per LatticeECP3 Devices Package ECP3-17 256 ftBGA 1 484 ftBGA 1 672 ftBGA — 1156 ftBGA — SERDES Block A SERDES receiver channel may receive the serial differential data stream, equalize the signal, perform Clock and Data Recovery (CDR) and de-serialize the data stream before passing the 8- or 10-bit data to the PCS logic. The SERDES transmitter channel may receive the parallel 8- or 10-bit data, serialize the data and transmit the serial bit stream through the differential drivers ...

  • Page 50

    ... Lattice Semiconductor The ispLEVER design tools from Lattice support all modes of the PCS. Most modes are dedicated to applications associated with a specific industry standard data protocol. Other more general purpose modes allow users to define their own operation. With ispLEVER, the user can define the mode for each quad in a design. ...

  • Page 51

    ... TransFR (Transparent Field Reconfiguration) TransFR I/O (TFR unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen dur- ing device configuration. This allows the device to be field updated with a minimum of system disruption and downtime ...

  • Page 52

    ... On-Chip Oscillator Every LatticeECP3 device has an internal CMOS oscillator which is used to derive a Master Clock (MCLK) for con- figuration. The oscillator and the MCLK run continuously and are available to user logic after configuration is com- pleted. The software default value of the MCLK is nominally 2.5MHz. Table 2-16 lists all the available MCLK frequencies ...

  • Page 53

    ... LatticeECP3 SERDES/PCS Usage Guide © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 54

    ... IH 0  V < V — IN CCIO  V  0.5V — CCIO IN CCIO 1, 2 Min. — ESD Stress HBM 1 CDM CDM 3-2 LatticeECP3 Family Data Sheet Typ. Max. Units — +/-1 — +/-1 18 — Typ. Max. Units — 8 Min. Units 1000 V 500 V 400 V mA ...

  • Page 55

    ... CCIO V = 1.2V (MAX 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 2 CCIO V = 1.2V (MAX 3-3 DC and Switching Characteristics LatticeECP3 Family Data Sheet Min. Typ. Max. — — 10 — — 150 -30 — -210 30 — 210 30 — — -30 — — — ...

  • Page 56

    ... Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the V 3. Frequency 0 MHz. 4. Pattern represents a “blank” configuration data file 85°C, power supplies at nominal voltage determine the LatticeECP3 peak start-up current data, use the Power Calculator tool in ispLEVER Parameter 3-4 DC and Switching Characteristics LatticeECP3 Family Data Sheet ...

  • Page 57

    ... Pre-emphasis adds 20mA to ICCA-OP data Over Recommended Operating Conditions Description current (per channel) current (per channel) current (per channel) current (per channel) current (per channel) 3-5 DC and Switching Characteristics LatticeECP3 Family Data Sheet Typ. Max. Units — — mA — — ...

  • Page 58

    ... HSTL15D_ I 1.425 2 2 HSTL18D_ 1.71 1. Inputs on chip. Outputs are implemented with the addition of external resistors. 2. For input voltage compatibility, refer to the "Mixed Voltage Support" section of TN1177, DC and Switching Characteristics LatticeECP3 Family Data Sheet V CCIO Typ. Max. Min. 3.3 3.465 — 2.5 2.625 — ...

  • Page 59

    ... REF - 0 0.2 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF 3-7 DC and Switching Characteristics LatticeECP3 Family Data Sheet Max. (V) Min. (V) I (mA) OL 20, 16, 0 0.4 CCIO 12 0 0.2 0.1 CCIO 20, 16, 0 0.4 CCIO 12 0 ...

  • Page 60

    ... Ohm 100 Ohm )/ 100 Ohm Driver Outputs Shorted to OD Each Other 3-8 DC and Switching Characteristics LatticeECP3 Family Data Sheet Min. Typ. Max. 0 — 2.4 0.05 — 2.35 +/-100 — — — — +/-10 — 1.38 1.60 0.9V 1.03 — 250 350 450 — ...

  • Page 61

    ... Lattice Semiconductor LVDS25E The top and bottom sides of LatticeECP3 devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. Figure 3-1. LVDS25E Output Termination Example VCCIO = 2.5V (± ...

  • Page 62

    ... Lattice Semiconductor BLVDS25 The LatticeECP3 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals ...

  • Page 63

    ... Lattice Semiconductor LVPECL33 The LatticeECP3 devices support the differential LVPECL standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals ...

  • Page 64

    ... Lattice Semiconductor RSDS25E The LatticeECP3 devices support differential RSDS and RSDSE standards. This standard is emulated using com- plementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input stan- dard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation ...

  • Page 65

    ... Lattice Semiconductor MLVDS25 The LatticeECP3 devices support the differential MLVDS standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for MLVDS standard implementation ...

  • Page 66

    ... Pseudo-Dual Port RAM 64x8 Pseudo-Dual Port RAM DSP Function 18x18 Multiplier (All Registers) 9x9 Multiplier (All Registers) 36x36 Multiply (All Registers Function 1, 2 Function 3-14 DC and Switching Characteristics LatticeECP3 Family Data Sheet -8 Timing Units 4.7 4.7 5.7 4.1 4.3 4.7 4.8 -8 Timing Units ...

  • Page 67

    ... Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The ispLEVER design tool can provide logic timing numbers at a particular temperature and voltage Function 3-15 DC and Switching Characteristics LatticeECP3 Family Data Sheet -8 Timing Units 200 400 MHz MHz ...

  • Page 68

    ... H ter Clock to Data Setup - PIO Input Regis- t SU_DEL ter with Data Input Delay Clock to Data Hold - PIO Input Regis- t H_DEL ter with Input Data Delay DC and Switching Characteristics LatticeECP3 Family Data Sheet Device Min. Max. Min. ECP3-150EA — 500 — ECP3-150EA 0.8 — ...

  • Page 69

    ... Lattice Semiconductor LatticeECP3 External Switching Characteristics (Continued) Over Recommended Commercial Operating Conditions Parameter Description Clock Frequency of I/O and PFU Reg- f MAX_IO ister General I/O Pin Parameters Using Dedicated Clock Input Primary Clock with PLL with Clock Injection Removal Setting t Clock to Output - PIO Output Register ECP3-150EA ...

  • Page 70

    ... Lattice Semiconductor LatticeECP3 External Switching Characteristics (Continued) Over Recommended Commercial Operating Conditions Parameter Description f DDRX1 Clock Frequency MAX_GDDR Generic DDRX1 Inputs with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX1_RX.DQS.Centered) Using DQS Pin for Clock Input Left, Right and Top for Data and Clock ...

  • Page 71

    ... Lattice Semiconductor LatticeECP3 External Switching Characteristics (Continued) Over Recommended Commercial Operating Conditions Parameter Description t Data Hold After CLK DVECLKGDDR f DDR/DDRX2 Clock Frequency MAX_GDDR Generic DDRX2 Inputs with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX2_RX.DQS.Centered) using DQS Pin for Clock Input ...

  • Page 72

    ... Lattice Semiconductor LatticeECP3 External Switching Characteristics (Continued) Over Recommended Commercial Operating Conditions Parameter Description Generic DDRX2 Output with Clock and Data (> 10 Bits Wide) Aligned at Pin (GDDRX2_TX.ECLK.Aligned) Left and Right Sides t Data Setup Before CLK DIBGDDR t Data Hold After CLK DIAGDDR ...

  • Page 73

    ... Lattice Semiconductor LatticeECP3 External Switching Characteristics (Continued) Over Recommended Commercial Operating Conditions Parameter Description f DDR2 Clock Frequency MAX_DDR2 DDR3 (Using PLL for SCLK) I/O Pin Parameters t Data Valid After DQS (DDR Read) DVADQ t Data Hold After DQS (DDR Read) DVEDQ t Data Valid Before DQS ...

  • Page 74

    ... Lattice Semiconductor Figure 3-6. Generic DDR/DDR2 (With Clock and Data Edges Aligned) t DIBGDDR CLK Data (TDAT, TCTL) t DIAGDDR RDTCLK Data (RDAT, RCTL) t DVACLKGDDR t Transmit Parameters t DIAGDDR t DIBGDDR Receive Parameters t DVACLKGDDR t DVECLKGDDR DVECLKGDDR 3-22 DC and Switching Characteristics LatticeECP3 Family Data Sheet ...

  • Page 75

    ... Figure 3-8. Generic DDR/DDR2 Parameters (With Clock Center on Data Window) CLOCK DATA t DVBCKGDDR t DVACKGDDR CLOCK DATA t SUGDDR t HGDDR Transmit Parameters t DQVAS t DQVBS Receive Parameters t DVADQ t t DVEDQ DVEDQ Transmit Parameters t DVACKGDDR t DVBCKGDDR Receive Parameters t SUGDDR t HGDDR 3-23 DC and Switching Characteristics LatticeECP3 Family Data Sheet ...

  • Page 76

    ... Setup Data to EBR Memory SUDATA_EBR t Hold Data to EBR Memory HDATA_EBR t Setup Address to EBR Memroy SUADDR_EBR t Hold Address to EBR Memory HADDR_EBR t Setup Write/Read Enable to PFU Memory SUWREN_EBR DC and Switching Characteristics LatticeECP3 Family Data Sheet Min. Max. Min. — 0.147 — — 0.273 — — 0.593 — ...

  • Page 77

    ... Internal parameters are characterized but not tested on every device. 2. Commercial timing numbers are shown. Industrial timing numbers are typically slower and can be extracted from the ispLEVER software. 3. DSP slice is configured in Multiply Add/Sub 18x18 mode. 4. The output register is in Flip-flop mode. DC and Switching Characteristics LatticeECP3 Family Data Sheet 1, 2 (Continued Min ...

  • Page 78

    ... Figure 3-10. Read/Write Mode with Input and Output Registers CLKA CSA WEA ADA t DIA DOA (Regs CO_EBR Mem(n) data from previous read output is only updated during a read cycle 3-26 DC and Switching Characteristics LatticeECP3 Family Data Sheet CO_EBR CO_EBR COO_EBR COO_EBR D0 D1 ...

  • Page 79

    ... Data from Prev Read DOA or Write Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Three consecutive writes ACCESS ACCESS ACCESS D0 D1 3-27 DC and Switching Characteristics LatticeECP3 Family Data Sheet ACCESS ...

  • Page 80

    ... LVCMOS, VCCIO = 1.2V PCI33 PCI, VCCIO = 3.0V Output Adjusters LVDS25E LVDS, Emulated, VCCIO = 2.5V LVDS25 LVDS, VCCIO = 2.5V BLVDS25 BLVDS, Emulated, VCCIO = 2.5V MLVDS25 MLVDS, Emulated, VCCIO = 2.5V DC and Switching Characteristics LatticeECP3 Family Data Sheet Description 3- Units 0.03 -0.01 -0.03 ns 0.03 ...

  • Page 81

    ... LVCMOS 1.8 4mA drive, fast slew rate LVCMOS18_8mA LVCMOS 1.8 8mA drive, fast slew rate LVCMOS18_12mA LVCMOS 1.8 12mA drive, fast slew rate LVCMOS18_16mA LVCMOS 1.8 16mA drive, fast slew rate DC and Switching Characteristics LatticeECP3 Family Data Sheet (Continued) Description 3- Units ...

  • Page 82

    ... Not all I/O standards and drive strengths are supported for all banks. See the Architecture section of this data sheet for details. 5. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the ispLEVER software. DC and Switching Characteristics LatticeECP3 Family Data Sheet (Continued) ...

  • Page 83

    ... Lattice Semiconductor LatticeECP3 Maximum I/O Buffer Speed Buffer Maximum Input Frequency LVDS25 MLVDS25 BLVDS25 PPLVDS TRLVDS Mini LVDS LVPECL33 HSTL18 (all supported classed) HSTL15 SSTL33 (all supported classed) SSTL25 (all supported classed) SSTL18 (all supported classed) LVTTL33 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 ...

  • Page 84

    ... Lattice Semiconductor LatticeECP3 Maximum I/O Buffer Speed (Continued) Buffer PCI33 1. These maximum speeds are characterized but not tested on every device. 2. Maximum I/O speed for differential output standards emulated with resistors depends on the layout. 3. LVCMOS timing is measured with the load specified in the Switching Test Conditions table of this document. ...

  • Page 85

    ... OUT f < 100MHz OUT MHz 25 to 500 MHz 90% to 90% 10% to 10% f > 4MHz. For PFD f < 4MHz. PFD 3-33 DC and Switching Characteristics LatticeECP3 Family Data Sheet Clock Min. Typ. Max. Edge clock 2 — 500 Primary clock 2 — 420 Edge clock 4 — ...

  • Page 86

    ... Condition Edge Clock Primary Clock Primary Clock < 250MHz Primary Clock 250MHz Edge Clock Primary Clock < 250MHz Primary Clock  250MHz Edge Clock 3-34 DC and Switching Characteristics LatticeECP3 Family Data Sheet Min. Typ. Max. 133 — 500 133 — 500 133 — ...

  • Page 87

    ... FPGA logic active, I/Os around SERDES pins quiet, 3-35 LatticeECP3 Family Data Sheet Min. Typ. Max. Units 1150 1440 1730 mV, p-p 1080 1350 1620 mV, p-p 1000 ...

  • Page 88

    ... SERDES Bridge Recovered Clock Deserializer Polarity 1:8/1:10 Adjust BYPASS BYPASS T3 Encoder Polarity Adjust BYPASS BYPASS 3-36 DC and Switching Characteristics LatticeECP3 Family Data Sheet Avg. Max. Fixed Bypass 3 5 — 1 — — — — — — — —  ...

  • Page 89

    ... DC and Switching Characteristics LatticeECP3 Family Data Sheet Min. Typ. Max. — — 136 — — 144 — — 160 — ...

  • Page 90

    ... Gbps Periodic 622 Mbps Periodic 155 Mbps Note: Values are measured with PRBS 2 quiet, voltages are nominal, room temperature. DC and Switching Characteristics LatticeECP3 Family Data Sheet Condition Min. 600 mV differential eye — 600 mV differential eye — 600 mV differential eye — ...

  • Page 91

    ... Guide. 3-39 DC and Switching Characteristics LatticeECP3 Family Data Sheet Typ. Max. — 320 — 1000 — V mV, p-p CCA mV, p-p — 2*V CCA differential — ...

  • Page 92

    ... Values are measured at 2.5 Gbps. 2. Measured with external AC-coupling on the receiver. 3.Not in compliance with PCI Express 1.1 standard. Over Recommended Operating Conditions Description Test Conditions 3-40 DC and Switching Characteristics LatticeECP3 Family Data Sheet Min Typ Max 399.88 400 400.12 0.8 1 ...

  • Page 93

    ... Values are measured at 2.5 Gbps. Over Recommended Operating Conditions Test Conditions 20%-80% Over Recommended Operating Conditions Test Conditions From 100 MHz to 3.125 GHz From 100 MHz to 3.125 GHz 3-41 DC and Switching Characteristics LatticeECP3 Family Data Sheet Min. Typ. Max. — 80 — 80 100 120 — — ...

  • Page 94

    ... Note: The sinusoidal jitter tolerance is measured with at least 0.37UIpp of Deterministic jitter (Dj) and the sum of Dj and Rj (random jitter least 0.55UIpp. Therefore, the sum of Dj, Rj and Sj (sinusoidal jitter least 0.65UIpp (Dj = 0.37 0.18 0.1). DC and Switching Characteristics LatticeECP3 Family Data Sheet 8.5UI 20dB/dec Data_rate/ ...

  • Page 95

    ... Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. 4. Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization is enabled. 5. Values are measured at 2.5 Gbps. DC and Switching Characteristics LatticeECP3 Family Data Sheet Test Conditions Min. Typ. ...

  • Page 96

    ... Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization is enabled. 5. Values are measured at 1.25 Gbps. Description Test Conditions 20%-80% Test Conditions From 100 MHz to 1.25 GHz From 100 MHz to 1.25 GHz 3-44 DC and Switching Characteristics LatticeECP3 Family Data Sheet Min. Typ. Max. — 80 — 80 100 120 — ...

  • Page 97

    ... Jitter is defined in accordance with SMPTE RP1 184-1996 as: jitter at an equipment output in the absence of input jitter. 3. All Tx jitter is measured at the output of an industry standard cable driver; connection to the cable driver is via a 50 ohm impedance differen- tial signal from the Lattice SERDES device. 4. The cable driver drives: RL=75 ohm, AC-coupled at 270, 1485, or 2970 Mbps, RREFLVL=RREFPRE=4.75kohm 1%. ...

  • Page 98

    ... Output buffers must drive a translation device. Max. speed is 2Gbps. If translation device does not modify rise/fall time, the maximum speed is 1.5Gbps. 2. Input buffers must be AC coupled in order to support the 3.3V common mode. Generally, HDMI inputs are terminated by an external cable equalizer before data/clock is forwarded to the LatticeECP3 device Description ...

  • Page 99

    ... OH measurement. SDO OL SDO *Risetime compensation. Passband Ripple < ±1dB >1/10 f 10Hz Jitter Frequency 3-47 DC and Switching Characteristics LatticeECP3 Family Data Sheet V DDSD 75Ω test eqpt. (atteunation 0dB) 1.0µ DDSD 5.5-30pF* 50 test eqpt. (atteunation 3.5dB) 24.9Ω 1.0µ ...

  • Page 100

    ... Lattice Semiconductor LatticeECP3 sysCONFIG Port Timing Specifications Parameter POR, Configuration Initialization, and Wakeup Time from the Application the Last to Cross the POR Trip Point) to the Rising Edge of ICFG INITN t Time from t to the Valid Master MCLK VMC ICFG t PROGRAMN Low Time to Start Configuration ...

  • Page 101

    ... Lattice Semiconductor LatticeECP3 sysCONFIG Port Timing Specifications (Continued) Parameter t HOLDN Low Hold Time (Relative to CCLK) CHHH Master and Slave SPI (Continued) t HOLDN High Hold Time (Relative to CCLK) CHHL t HOLDN High Setup Time (Relative to CCLK) HHCH t HOLDN to Output High-Z HLQZ t HOLDN to Output Low-Z ...

  • Page 102

    ... Figure 3-19. sysCONFIG Slave Serial Port Timing CCLK (input) DIN DOUT t BSCL t SUCS t SUWD t t HCBDI SUCBDI Byte 0 Byte 1 Byte 2 t SUMCDI t SSCL t SUSCDI 3-50 DC and Switching Characteristics LatticeECP3 Family Data Sheet t BSCYC t BSCH t HCS t HWD t DCB Byte n t HMCDI t CODO t SSCH t HSCDI t CODO ...

  • Page 103

    ... Time taken from Device Master Mode (SPI, SPIm). 3. The CFG pins are normally static (hard wired). Figure 3-21. sysCONFIG Port Timing t ICFG t VMC Valid whichever is the last to cross the POR trip point. CCAUX CCIO8 3-51 DC and Switching Characteristics LatticeECP3 Family Data Sheet ...

  • Page 104

    ... INITN DONE CCLK CFG[2:0] 1 USER I/O 1. The CFG pins are normally static (hard wired) Figure 3-23. Wake-Up Timing PROGRAMN INITN DONE CCLK USER I/O t PRGMRJ t DPPINIT t DINITD t IODISS Wake-Up t MWC t IOENSS 3-52 DC and Switching Characteristics LatticeECP3 Family Data Sheet t DINIT Valid ...

  • Page 105

    ... Lattice Semiconductor Figure 3-24. Master SPI Configuration Waveforms Capture CR0 VCC PROGRAMN DONE INITN CSSPIN CCLK SISPI SOSPI DC and Switching Characteristics Capture CFGx … … Opcode Address 3-53 LatticeECP3 Family Data Sheet … 127 128 Ignore Valid Bitstream ...

  • Page 106

    ... Over Recommended Operating Conditions Parameter t t BTS BTH t BTCPL t t BTCOEN BTCRH t BTCRS Data Captured t BTUPOEN 3-54 DC and Switching Characteristics LatticeECP3 Family Data Sheet Min Max — — 20 — 20 — 10 — 8 — 50 — — 10 — 10 — — 25 — — 25 — 25 — ...

  • Page 107

    ... Includes Test Fixture and Probe Capacitance    1M  1M  100  100 3-55 DC and Switching Characteristics LatticeECP3 Family Data Sheet Test Poi nt C Timing Ref. L LVCMOS 3.3 = 1.5V LVCMOS 2 CCIO 0pF LVCMOS 1 CCIO LVCMOS 1 CCIO LVCMOS 1 ...

  • Page 108

    ... CCO V Input differential voltage ID V Input common mode voltage ICM V Termination supply voltage CCO R Termination resistance (off-chip) T Note: LatticeECP3 only supports the TRLVDS receiver. Transmitter Current Source Mini LVDS Parameter Symbol Z Single-ended PCB trace impedance O R Differential termination resistance T V Output voltage, differential, |V ...

  • Page 109

    ... Over Recommended Operating Conditions Min. Typ. 3.14 3.3 2.25 2.5 100 0.2 130 0.5 0.8 Over Recommended Operating Conditions Description = 100 ohms T 3-57 DC and Switching Characteristics LatticeECP3 Family Data Sheet Max. Units 3.47 V 2.75 V 400 mV 2.3 V 400 mV 1.4 V Min. Typ. Max. ...

  • Page 110

    ... PCLK[T, C][n:0]_[3:0] © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 111

    ... Parallel configuration I/O. Slave SPI data output. Open drain during configura- I/O tion. I/O Parallel configuration I/O. Open drain during configuration. Parallel configuration I/O. SPI/SPIm data input. Open drain during configura- I/O tion. 4-2 Pinout Information LatticeECP3 Family Data Sheet Description ...

  • Page 112

    ... High-speed output, negative channel m I Negative Reference Clock Input I High-speed input, positive channel m O High-speed output, positive channel m I Positive Reference Clock Input — Output buffer power supply, channel m (1.2V/1.5) — Input buffer power supply, channel m (1.2V/1.5V) 4-3 Pinout Information LatticeECP3 Family Data Sheet Description ...

  • Page 113

    ... P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] For Top Edge of the Device P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] Note: “n” row PIC number. LatticeECP3 Family Data Sheet DDR Strobe (DQS) and PIO Within PIC Data (DQ) Pins ...

  • Page 114

    ... Total Single-Ended User I/O VCC VCCAUX VTT VCCA VCCPLL Bank 0 Bank 1 Bank 2 VCCIO Bank 3 Bank 6 Bank 7 Bank 8 VCCJ TAP GND, GNDIO NC 1 Reserved SERDES Miscellaneous Pins Total Bonded Pins LatticeECP3 Family Data Sheet ECP3-17EA ECP3-35EA 256 484 256 484 ftBGA fpBGA ftBGA fpBGA fpBGA ...

  • Page 115

    ... Bank 3 Differential I/O per Bank Bank 6 Bank 7 Bank 8 Bank 0 Bank 1 Bank 2 DDR Groups Bonded per Bank 3 Bank Bank 6 Bank 7 Configuration Bank 8 SERDES Quads 1. These pins must remain floating on the board. LatticeECP3 Family Data Sheet ECP3-17EA 256 ftBGA 484 fpBGA 256 ftBGA ...

  • Page 116

    ... Bank 0 Bank 1 Bank 2 Total Single-Ended/ Total Differential I/O Bank 3 per Bank Bank 6 Bank 7 Bank 8 Bank 0 Bank 1 Bank 2 DDR Groups Bonded Bank 3 per Bank Bank 6 Bank 7 Configuration Bank 8 SERDES Quads LatticeECP3 Family Data Sheet ECP3-70E 1156 484 fpBGA 672 fpBGA fpBGA ...

  • Page 117

    ... Bank 8 Total Single-Ended User I/O VCC VCCAUX VTT VCCA VCCPLL Bank 0 Bank 1 Bank 2 VCCIO Bank 3 Bank 6 Bank 7 Bank 8 VCCJ TAP GND, GNDIO NC 1 Reserved SERDES Miscellaneous Pins Total Bonded Pins LatticeECP3 Family Data Sheet ECP3-95E/EA 484 672 1156 fpBGA fpBGA fpBGA ...

  • Page 118

    ... Pinout Information LatticeECP3 Family Data Sheet ECP3-95EA ECP3-150EA 672 1156 672 fpBGA fpBGA fpBGA 60/30 86/43 60/30 48/24 78/39 ...

  • Page 119

    ... Thermal Management document • TN1181, Power Consumption and Management for LatticeECP3 Devices • Power Calculator tool included with the Lattice ispLEVER design tool standalone download from  www.latticesemi.com/software LatticeECP3 Family Data Sheet and in the Lattice ispLEVER Design Planner software. To cre- 4-10 ...

  • Page 120

    ... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com LatticeECP3 Family Data Sheet LFE3 – XXX XX – X XXXXXX X Commercial Industrial ECP3 ...

  • Page 121

    ... LFE3-35EA-8FTN256C 1.2V LFE3-35EA-6FN484C 1.2V LFE3-35EA-7FN484C 1.2V LFE3-35EA-8FN484C 1.2V LFE3-35EA-6FN672C 1.2V LFE3-35EA-7FN672C 1.2V LFE3-35EA-8FN672C 1.2V Part Number Voltage LFE3-70EA-6FN484C 1.2V LFE3-70EA-7FN484C 1.2V LFE3-70EA-8FN484C 1.2V LFE3-70EA-6FN672C 1.2V LFE3-70EA-7FN672C 1.2V LFE3-70EA-8FN672C 1.2V LFE3-70EA-6FN1156C 1.2V LFE3-70EA-7FN1156C 1.2V LFE3-70EA-8FN1156C 1.2V LatticeECP3 Family Data Sheet Commercial Grade ...

  • Page 122

    ... LFE3-95EA-6FN1156C 1.2V LFE3-95EA-7FN1156C 1.2V LFE3-95EA-8FN1156C 1.2V Part Number Voltage 1 LFE3-95E-6FN484C 1.2V 1 LFE3-95E-7FN484C 1.2V 1 LFE3-95E-8FN484C 1.2V 1 LFE3-95E-6FN672C 1.2V 1 LFE3-95E-7FN672C 1.2V 1 LFE3-95E-8FN672C 1.2V 1 LFE3-95E-6FN1156C 1.2V 1 LFE3-95E-7FN1156C 1.2V 1 LFE3-95E-8FN1156C 1.2V 1.This device has associated errata. View Part Number Voltage LFE3-150EA-6FN672C 1.2V LFE3-150EA-7FN672C 1.2V LFE3-150EA-8FN672C 1 ...

  • Page 123

    ... LFE3-150EA-8FN1156CTW* *Note: Specifications for the LFE3-150EA-spFNpkgCTW and LFE3-150EA-spFNpkgITW devices, (where sp is the speed and pkg is the package), are the same as the LFE3-150EA-spFNpkgC and LFE3-150EA-spFNpkgI devices respectively, except as specified below. • The CTC (Clock Tolerance Circuit) inside the SERDES hard PCS in the TW device is not functional but it can be bypassed and implemented in soft IP. • ...

  • Page 124

    ... LFE3-35EA-8FTN256I 1.2V LFE3-35EA-6FN484I 1.2V LFE3-35EA-7FN484I 1.2V LFE3-35EA-8FN484I 1.2V LFE3-35EA-6FN672I 1.2V LFE3-35EA-7FN672I 1.2V LFE3-35EA-8FN672I 1.2V Part Number Voltage LFE3-70EA-6FN484I 1.2V LFE3-70EA-7FN484I 1.2V LFE3-70EA-8FN484I 1.2V LFE3-70EA-6FN672I 1.2V LFE3-70EA-7FN672I 1.2V LFE3-70EA-8FN672I 1.2V LFE3-70EA-6FN1156I 1.2V LFE3-70EA-7FN1156I 1.2V LFE3-70EA-8FN1156I 1.2V LatticeECP3 Family Data Sheet Industrial Grade ...

  • Page 125

    ... View Part Number Voltage LFE3-95EA-6FN484I 1.2V LFE3-95EA-7FN484I 1.2V LFE3-95EA-8FN484I 1.2V LFE3-95EA-6FN672I 1.2V LFE3-95EA-7FN672I 1.2V LFE3-95EA-8FN672I 1.2V LFE3-95EA-6FN1156I 1.2V LFE3-95EA-7FN1156I 1.2V LFE3-95EA-8FN1156I 1.2V Part Number Voltage 1 LFE3-95E-6FN484I 1.2V 1 LFE3-95E-7FN484I 1.2V 1 LFE3-95E-8FN484I 1.2V 1 LFE3-95E-6FN672I 1.2V 1 LFE3-95E-7FN672I 1.2V 1 LFE3-95E-8FN672I 1.2V 1 LFE3-95E-6FN1156I 1.2V 1 LFE3-95E-7FN1156I 1.2V 1 LFE3-95E-8FN1156I 1 ...

  • Page 126

    ... LFE3-150EA-8FN1156ITW* *Note: Specifications for the LFE3-150EA-spFNpkgCTW and LFE3-150EA-spFNpkgITW devices, (where sp is the speed and pkg is the package), are the same as the LFE3-150EA-spFNpkgC and LFE3-150EA-spFNpkgI devices respectively, except as specified below. • The CTC (Clock Tolerance Circuit) inside the SERDES hard PCS in the TW device is not functional but it can be bypassed and implemented in soft IP. • ...

  • Page 127

    ... PCI: www.pcisig.com © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 128

    ... DC and Switching Characteristics © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 129

    ... Added footnote 2 to On-Chip Programmable Termination Options for Input Modes table. Corrected Per Quadrant Primary Clock Selection figure. Modified -8 Timing data for 1024x18 True-Dual Port RAM (Read-Before- Write, EBR Output Registers) Added ESD Performance table. LatticeECP3 External Switching Characteristics table - updated data for DIBGDDR W_PRI ...

  • Page 130

    ... Updated Single-Ended DC table. Updated TRLVDS table and figure. Updated Serial Data Input Specifications table. Updated HDMI Transmit and Receive table. Added LFE3-150EA “TW” devices and footnotes to the Commercial and Industrial tables. Added Read-Before-Write information. Added footnote #6 to Maximum I/O Buffer Speed table. ...