LFE3-95E-PCIE-DKN Lattice, LFE3-95E-PCIE-DKN Datasheet - Page 87

• Manufacturer Part Number: LFE3-95E-PCIE-DKN
• Description: MCU, MPU & DSP Development Tools LatticeECP3 PCI Express Dev Kit
• Manufacturer: Lattice

Specifications of LFE3-95E-PCIE-DKN

• Processor To Be Evaluated: LFE3-95EA-x
• Processor Series: LatticeECP3
• Interface Type: SPI
• Operating Supply Voltage: 1.2 V to 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
SERDES High-Speed Data Transmitter
Table 3-6. Serial Output Timing and Levels
Table 3-7. Channel Output Jitter
V
V
V
V
V
V
V
V
V
V
T
T
Z
R
T
T
1. All measurements are with 50 ohm impedance.
2. See TN1176,
3. Inter-quad skew is between all SERDES channels on the device and requires the use of a low skew internal reference clock.
TX-R
TX-F
TX-OI-SE
TX-INTRASKEW
TX-INTERSKEW
TX-DIFF-P-P-1.44
TX-DIFF-P-P-1.35
TX-DIFF-P-P-1.26
TX-DIFF-P-P-1.13
TX-DIFF-P-P-1.04
TX-DIFF-P-P-0.92
TX-DIFF-P-P-0.87
TX-DIFF-P-P-0.78
TX-DIFF-P-P-0.64
OCM
LTX-RL
Symbol
Deterministic
Random
Total
Deterministic
Random
Total
Deterministic
Random
Total
Deterministic
Random
Total
Deterministic
Random
Total
Note: Values are measured with PRBS 2
reference clock @ 10X mode.
Description
3
LatticeECP3 SERDES/PCS Usage Guide
Differential swing (1.44V setting)
Differential swing (1.35V setting)
Differential swing (1.26V setting)
Differential swing (1.13V setting)
Differential swing (1.04V setting)
Differential swing (0.92V setting)
Differential swing (0.87V setting)
Differential swing (0.78V setting)
Differential swing (0.64V setting)
Output common mode voltage
Rise time (20% to 80%)
Fall time (80% to 20%)
Output Impedance 50/75/HiZ Ohms 
(single ended)
Return loss (with package)
Lane-to-lane TX skew within a 
SERDES quad block (intra-quad)
Lane-to-lane skew between SERDES
quad blocks (inter-quad)
3.125 Gbps
3.125 Gbps
3.125 Gbps
2.5Gbps
2.5Gbps
2.5Gbps
1.25 Gbps
1.25 Gbps
1.25 Gbps
622 Mbps
622 Mbps
622 Mbps
250 Mbps
250 Mbps
250 Mbps
Frequency
Description
7
-1, all channels operating, FPGA logic active, I/Os around SERDES pins quiet,
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
Min.
—
—
—
—
—
—
—
—
—
for actual binary settings and the min-max range.
—
—
—
—
—
—
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
3-35
1
Frequency
—
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC and Switching Characteristics
LatticeECP3 Family Data Sheet
V
-20%
1150
1080
1000
-0.75
Min.
585
480
145
145
840
780
690
650
CCOB
10
—
—
Max.
0.17
0.35
0.20
0.22
0.10
0.10
0.25
0.17
0.35
0.10
0.24
0.20
0.24
0.18
0.24
V
50/75/
-0.60
1440
1350
1260
1130
1040
Typ.
Hi Z
920
870
780
640
CCOB
185
185
—
—
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
1UI +200
Units
V
+20%
Max.
1730
1620
1510
1420
1300
1150
1090
-0.45
975
800
265
265
200
CCOB
mV, p-p
mV, p-p
mV, p-p
mV, p-p
mV, p-p
mV, p-p
mV, p-p
mV, p-p
mV, p-p
Ohms
Units
dB
ps
ps
ps
ps
V