LFE3-95E-PCIE-DKN Lattice, LFE3-95E-PCIE-DKN Datasheet - Page 91
LFE3-95E-PCIE-DKN
Manufacturer Part Number
LFE3-95E-PCIE-DKN
Description
MCU, MPU & DSP Development Tools LatticeECP3 PCI Express Dev Kit
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672CTW.pdf
(130 pages)
Specifications of LFE3-95E-PCIE-DKN
Processor To Be Evaluated
LFE3-95EA-x
Processor Series
LatticeECP3
Interface Type
SPI
Operating Supply Voltage
1.2 V to 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 91 of 130
- Download datasheet (3Mb)
Table 3-12. External Reference Clock Specification (refclkp/refclkn)
Lattice Semiconductor
SERDES External Reference Clock
The external reference clock selection and its interface are a critical part of system applications for this product.
Table 3-12 specifies reference clock requirements, over the full range of operating conditions.
Figure 3-13. SERDES External Reference Clock Waveforms
F
F
V
V
V
V
D
T
T
Z
C
1. The signal swing for a single-ended input clock must be as large as the p-p differential swing of a differential input clock to get the same gain
2. When AC coupled, the input common mode range is determined by:
3. Measured at 50% amplitude.
4. Depending on the application, the PLL_LOL_SET and CDR_LOL_SET control registers may be adjusted for other tolerance values as
REF
REF-PPM
REF-R
REF-F
REF-IN-TERM-DIFF
REF-IN-SE
REF-IN-DIFF
REF-IN
REF-CM-AC
REF
REF-IN-CAP
at the input receiver. Lower swings for the clock may be possible, but will tend to increase jitter.
(Min input level) + (Peak-to-peak input swing)/2
described in TN1176,
Symbol
Frequency range
Frequency tolerance
Input swing, single-ended clock
Input swing, differential clock
Input levels
Input common mode range (AC coupled)
Duty cycle
Rise time (20% to 80%)
Fall time (80% to 20%)
Differential input termination
Input capacitance
LatticeECP3 SERDES/PCS Usage
3
Description
4
(Input common mode voltage)
1
Guide.
2
3-39
-1000
0.125
-20%
Min.
200
200
200
200
15
40
—
0
(Max input level) - (Peak-to-peak input swing)/2
DC and Switching Characteristics
100/2K
Typ.
LatticeECP3 Family Data Sheet
500
500
—
—
—
—
—
—
—
—
V
CCA
2*V
+20%
V
V
Max.
1000
1000
1000
320
CCA
CCA
60
7
CCA
+ 0.3
differential
mV, p-p
mV, p-p
Ohms
Units
MHz
ppm
pF
ps
ps
%
V
V
Related parts for LFE3-95E-PCIE-DKN
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 490 I/O 8 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 380 I/O 7 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 295 I/O 7 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 380 I/O 6 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 490 I/O 6 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 295 I/O 8 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 490 I/O 8 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 380 I/O 8 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 490 I/O 6 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 295 I/O 6 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 490 I/O 7 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 295 I/O 8 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 490 I/O 7 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 380 I/O 6 Speed
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 92K LUTs, 295 I/O 7 Speed
Manufacturer:
Lattice