PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 280

16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE

PIC24FJ64GB002-I/SS

Manufacturer Part Number
PIC24FJ64GB002-I/SS
Description
16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
Manufacturer
Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

Processor Series
PIC24
Core
PIC24F
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
8192 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SSOP-28
Development Tools By Supplier
MPLAB Integrated Development Environment
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
300 mA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ64GB002-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC24FJ64GB002-I/SS
0
PIC24FJ64GB004 FAMILY
REGISTER 26-1:
DS39940D-page 280
bit 23
bit 15
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 23-16
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
Note 1:
FWDTEN
R/PO-1
U-1
r-x
r
The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be
modified while connected through the JTAG interface.
Unimplemented: Read as ‘1’
Reserved: The value is unknown; program as ‘0’
JTAGEN: JTAG Port Enable bit
1 = JTAG port is enabled
0 = JTAG port is disabled
GCP: General Segment Program Memory Code Protection bit
1 = Code protection is disabled
0 = Code protection is enabled for the entire program memory space
GWRP: General Segment Code Flash Write Protection bit
1 = Writes to program memory are allowed
0 = Writes to program memory are disabled
DEBUG: Background Debugger Enable bit
1 = Device resets into Operational mode
0 = Device resets into Debug mode
Unimplemented: Read as ‘1’
ICS<1:0>: Emulator Pin Placement Select bits
11 = Emulator functions are shared with PGEC1/PGED1
10 = Emulator functions are shared with PGEC2/PGED2
01 = Emulator functions are shared with PGEC3/PGED3
00 = Reserved; do not use
FWDTEN: Watchdog Timer Enable bit
1 = Watchdog Timer is enabled
0 = Watchdog Timer is disabled
WINDIS: Windowed Watchdog Timer Disable bit
1 = Standard Watchdog Timer is enabled
0 = Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’
Unimplemented: Read as ‘1’
FWPSA: WDT Prescaler Ratio Select bit
1 = Prescaler ratio of 1:128
0 = Prescaler ratio of 1:32
JTAGEN
WINDIS
R/PO-1
R/PO-1
U-1
CW1: FLASH CONFIGURATION WORD 1
(1)
r = Reserved bit
PO = Program Once bit
R/PO-1
GCP
U-1
U-1
(1)
FWPSA
R/PO-1
R/PO-1
GWRP
U-1
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
WDTPS3
DEBUG
R/PO-1
R/PO-1
U-1
WDTPS2
R/PO-1
U-1
U-1
 2010 Microchip Technology Inc.
‘0’ = Bit is cleared
WDTPS1
R/PO-1
R/PO-1
ICS1
U-1
WDTPS0
R/PO-1
R/PO-1
ICS0
U-1
bit 16
bit 8
bit 0

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