ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 10

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

ISP1582_8
Product data sheet
7.1 DMA interface, DMA handler and DMA registers
7.2 Hi-Speed USB transceiver
7.3 MMU and integrated RAM
7.4 Microcontroller interface and microcontroller handler
7.5 OTG SRP module
The ISP1582 operates on a 12 MHz crystal oscillator. An integrated 40
multiplier generates the internal sampling clock of 480 MHz.
The DMA block can be subdivided into two blocks: DMA handler and DMA interface.
The firmware writes to the DMA Command register to start a DMA transfer (see
The handler interfaces to the same FIFO (internal RAM) as used by the USB core. On
receiving the DMA command, the DMA handler directs the data from the endpoint FIFO to
the external DMA device or from the external DMA device to the endpoint FIFO.
The DMA interface configures the timing and the DMA handshake. Data can be
transferred using either the DIOR and DIOW strobes or by the DACK and DREQ
handshakes. DMA configurations are set up by writing to the DMA Configuration register
(see
Remark: The DMA endpoint buffer length must be a multiple of 4 bytes.
For details on DMA registers, see
The analog transceiver directly interfaces to the USB cable through integrated termination
resistors. The high-speed transceiver requires an external resistor (12.0 k
between pin RREF and ground to ensure an accurate current mirror that generates the
Hi-Speed USB current drive. A full-speed transceiver is integrated as well. This makes the
ISP1582 compliant to Hi-Speed USB and Original USB, supporting both the high-speed
and full-speed physical layers. After automatic speed detection, the ST-NXP Wireless
Serial Interface Engine (SIE) sets the transceiver to use either high-speed or full-speed
signaling.
The Memory Management Unit (MMU) manages the access to the integrated RAM that is
shared by the USB, microcontroller handler and DMA handler. Data from the USB bus is
stored in the integrated RAM, which is cleared only when the microcontroller has read the
corresponding endpoint, or the DMA controller has written all data from the RAM of the
corresponding endpoint to the DMA bus. The OUT endpoint buffer can also be forcibly
cleared by setting bit CLBUF in the Control Function register. A total of 8 kB RAM is
available for buffering.
The microcontroller handler allows the external microcontroller or microprocessor to
access the register set in the ST-NXP Wireless SIE, as well as the DMA handler. The
initialization of the DMA configuration is done through the microcontroller handler.
The OTG supplement defines a Session Request Protocol (SRP), which allows a
B-device to request the A-device to turn on V
the A-device, which may be battery-powered, to conserve power by turning off V
there is no bus activity while still providing a means for the B-device to initiate bus activity.
Table 49
and
Table
Rev. 08 — 22 January 2009
50).
Section
8.4.
BUS
and start a session. This protocol allows
Hi-Speed USB peripheral controller
© ST-NXP Wireless 2009. All rights reserved.
ISP1582
PLL clock
1 %)
Table
BUS
when
9 of 67
44).