ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 35

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ISP1582BS,557

Manufacturer Part Number
ISP1582BS,557
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ISP1582BS,557

Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
56
Lead Free Status / RoHS Status
Compliant
Table 37.
Table 39.
ISP1582_8
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Buffer Status register: bit allocation
Endpoint MaxPacketSize register: bit allocation
8.3.6 Endpoint MaxPacketSize register (address: 04h)
R/W
15
7
7
0
0
-
-
-
-
-
-
Remark: For endpoint IN data transfer, firmware must ensure a 200 ns delay between
writing of the data packet and reading the Buffer Status register. For endpoint OUT data
transfer, firmware must also ensure a 200 ns delay between receiving the endpoint
interrupt and reading the Buffer Status register. For more information, refer to
“Using ISP1582/3 in a composite device application with alternate settings
Table 37
Table 38.
This register determines the maximum packet size for all endpoints, except set-up token
buffer, control IN and control OUT. The register contains 2 bytes, and the bit allocation is
given in
Each time the register is written, the Buffer Length register of the corresponding endpoint
is re-initialized to the FFOSZ field value. Bits NTRANS control the number of transactions
allowed in a single microframe (for high-speed isochronous and interrupt endpoints only).
Bit
7 to 2
1 to 0
reserved
R/W
14
6
6
0
0
-
-
-
-
-
-
Table
shows the bit allocation of the Buffer Status register.
Symbol
-
BUF[1:0]
Buffer Status register: bit description
39.
R/W
13
5
5
0
0
-
-
-
-
-
-
Rev. 08 — 22 January 2009
Description
reserved
Buffer:
00 — The buffers are not filled.
01 — One of the buffers is filled.
10 — One of the buffers is filled.
11 — Both the buffers are filled.
reserved
R/W
R/W
12
4
0
0
4
0
0
-
-
-
NTRANS[1:0]
FFOSZ[7:0]
R/W
R/W
11
3
0
0
3
0
0
-
-
-
Hi-Speed USB peripheral controller
R/W
R/W
10
2
0
0
2
0
0
-
-
-
FFOSZ[10:8]
© ST-NXP Wireless 2009. All rights reserved.
BUF1
R/W
R/W
R
1
0
0
9
0
0
1
0
0
ISP1582
(AN10071)”.
Ref. 3
BUF0
R/W
R/W
R
0
0
0
8
0
0
0
0
0
34 of 67

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