ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 40

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Table 47.
Table 49.
ISP1582_8
Product data sheet
Bit
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
DMA Transfer Counter register: bit allocation
DMA Configuration register: bit allocation
XFER_CNT
8.4.3 DMA Configuration register (address: 38h)
DIS_
R/W
15
-
-
-
R/W
R/W
R/W
R/W
7
0
0
31
23
15
0
0
0
0
0
0
7
0
0
Table 48.
This register defines the DMA configuration for GDMA mode. The DMA Configuration
register consists of 2 bytes. The bit allocation is given in
Bit
31 to 24
23 to 16
15 to 8
7 to 0
14
-
-
-
R/W
R/W
R/W
R/W
6
-
-
-
30
22
14
0
0
0
0
0
0
6
0
0
DMA Transfer Counter register: bit description
Symbol
DMACR4 = DMACR[31:24]
DMACR3 = DMACR[23:16]
DMACR2 = DMACR[15:8]
DMACR1 = DMACR[7:0]
reserved
13
5
R/W
R/W
R/W
R/W
-
-
-
-
-
-
29
21
13
0
0
0
0
0
0
5
0
0
Rev. 08 — 22 January 2009
DMACR3 = DMACR[23:16]
DMACR2 = DMACR[15:8]
DMACR1 = DMACR[7:0]
12
…continued
R/W
R/W
R/W
R/W
4
-
-
-
-
-
-
28
20
12
0
0
0
0
0
0
4
0
0
reserved
Description
DMA transfer counter byte 4 (MSByte)
DMA transfer counter byte 3
DMA transfer counter byte 2
DMA transfer counter byte 1 (LSByte)
R/W
11
R/W
R/W
R/W
R/W
3
0
0
-
-
-
27
19
11
0
0
0
0
0
0
3
0
0
MODE[1:0]
Hi-Speed USB peripheral controller
R/W
Table
R/W
R/W
R/W
R/W
10
2
0
0
26
18
10
-
-
-
0
0
0
0
0
0
2
0
0
49.
reserved
© ST-NXP Wireless 2009. All rights reserved.
R/W
R/W
R/W
R/W
25
17
9
1
-
-
-
-
-
-
0
0
0
0
9
0
0
1
0
0
ISP1582
WIDTH
R/W
R/W
R/W
R/W
R/W
24
16
8
0
1
1
0
0
0
0
8
0
0
0
0
0
-
-
-
39 of 67