ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 33

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Table 33.
ISP1582_8
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Data Port register: bit allocation
8.3.4 Buffer Length register (address: 1Ch)
R/W
R/W
15
0
0
7
0
0
Peripheral-to-host (IN endpoint): After each write action, an internal counter is auto
incremented by two to the next location in the TX FIFO. When all bytes are written (FIFO
byte count = endpoint MaxPacketSize), the buffer is automatically validated. The data
packet will then be sent on the next IN token. When it is necessary to validate the endpoint
whose byte count is less than MaxPacketSize, it can be done using the Control Function
register (bit VENDP) or the Buffer Length register.
Remark: The buffer can automatically be validated by using the Buffer Length register
(see
Host-to-peripheral (OUT endpoint): After each read action, an internal counter is auto
decremented by two to the next location in the RX FIFO. When all bytes are read, buffer
contents are automatically cleared. A new data packet can then be received on the next
OUT token. Buffer contents can also be cleared using the Control Function register (bit
CLBUF), when it is necessary to forcefully clear contents.
Remark: The delay time from the Write Endpoint Index register to the Read Data Port
register must be at least 190 ns.
Remark: The delay time from the Write Endpoint Index register to the Write Data Port
register must be at least 100 ns.
Table 34.
This register determines the current packet size (DATACOUNT) of the indexed endpoint
FIFO. The bit allocation is given in
The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint
MaxPacketSize register is written (see
required. After a bus reset, the Buffer Length register is made zero.
Bit
15 to 8 DATAPORT[15:8] data (upper byte)
7 to 0
Table
R/W
R/W
14
0
0
6
0
0
Symbol
DATAPORT[7:0]
Data Port register: bit description
35).
R/W
R/W
13
0
0
5
0
0
Rev. 08 — 22 January 2009
Description
data (lower byte)
R/W
R/W
DATAPORT[15:8]
12
DATAPORT[7:0]
0
0
4
0
0
Table
Table
35.
R/W
R/W
11
0
0
3
0
0
39). A smaller value can be written when
Hi-Speed USB peripheral controller
R/W
R/W
10
0
0
2
0
0
© ST-NXP Wireless 2009. All rights reserved.
R/W
R/W
9
0
0
1
0
0
ISP1582
R/W
R/W
8
0
0
0
0
0
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