ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 24
ISP1582BS,557
Manufacturer Part Number
ISP1582BS,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1582BS557.pdf
(68 pages)
Specifications of ISP1582BS,557
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
56
Lead Free Status / RoHS Status
Compliant
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Table 16.
Table 18.
[1]
ISP1582_8
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Value depends on the status of the V
Address register: bit allocation
Mode register: bit allocation
unchanged
CLKAON
8.2.2 Mode register (address: 0Ch)
unchanged
R/W
DEVEN
15
R
7
0
-
-
R/W
7
0
Table 17.
This register consists of 2 bytes (bit allocation: see
The Mode register controls resume, suspend and wake-up behavior, interrupt activity, soft
reset, clock signals and SoftConnect operation.
Table 19.
Bit
7
6 to 0 DEVADDR
Bit
15 to 10
9
8
SNDRSU
R/W
Symbol
DEVEN
[6:0]
14
R
6
0
0
-
-
R/W
6
0
0
Symbol
-
DMACLKON
VBUSSTAT
Address register: bit description
Mode register: bit description
BUS
pin.
GOSUSP
R/W
Description
Device Enable: Logic 1 enables the device. The device will not respond to
the host, unless this bit is set.
Device Address: This field specifies the USB device address.
13
R
5
0
0
R/W
-
-
5
0
0
Rev. 08 — 22 January 2009
reserved
Description
reserved
DMA Clock On:
0 — Power save mode; the DMA circuit will stop completely to save
power.
1 — Supply clock to the DMA circuit.
V
BUS
SFRESET
Pin Status: This bit reflects the V
R/W
12
R
R/W
4
0
0
-
-
4
0
0
DEVADDR[6:0]
GLINTENA
unchanged
R/W
11
R/W
R
3
0
-
-
3
0
0
Table
Hi-Speed USB peripheral controller
WKUPCS
R/W
R/W
10
18).
R
2
0
0
-
-
2
0
0
BUS
pin status.
unchanged
PWRON
© ST-NXP Wireless 2009. All rights reserved.
CLKON
DMA
R/W
R/W
R/W
9
0
0
1
0
1
0
0
ISP1582
VBUSSTAT
unchanged
SOFTCT
R/W
R/W
-
-
R
8
0
0
[1]
[1]
0
0
0
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