ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 30

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Table 28.
ISP1582_8
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Endpoint Index register: bit allocation
8.3.1 Endpoint Index register (address: 2Ch)
R/W
8.3 Data flow registers
7
-
-
reserved
Table 27.
The Endpoint Index register selects a target endpoint for register access by the
microcontroller. The register consists of 1 byte, and the bit allocation is shown in
The following registers are indexed:
For example, to access the OUT data buffer of endpoint 1 using the Data Port register, the
Endpoint Index register must be written first with 02h.
Remark: The Endpoint Index register and the DMA Endpoint register must not point to the
same endpoint, irrespective of IN and OUT.
Remark: The delay time from the Write Endpoint Index register to the Read Data Port
register must be at least 190 ns.
Remark: The delay time from the Write Endpoint Index register to the Write Data Port
register must be at least 100 ns.
Bit
7
6
5
4
3
2
1
0
•
•
•
•
•
•
Buffer length
Buffer status
Control function
Data port
Endpoint MaxPacketSize
Endpoint type
R/W
6
-
-
Symbol
IEVBUS
IEDMA
IEHS_STA
IERESM
IESUSP
IEPSOF
IESOF
IEBRST
Interrupt Enable register: bit description
EP0SETUP
unchanged
R/W
5
1
Rev. 08 — 22 January 2009
Description
Logic 1 enables interrupt for V
Logic 1 enables interrupt on the DMA Interrupt Reason register change
detection.
Logic 1 enables interrupt on detection of a high-speed status change.
Logic 1 enables interrupt on detection of a resume state.
Logic 1 enables interrupt on detection of a suspend state.
Logic 1 enables interrupt on detection of a pseudo SOF.
Logic 1 enables interrupt on detection of an SOF.
Logic 1 enables interrupt on detection of a bus reset.
R/W
4
0
0
R/W
3
0
0
ENDPIDX[3:0]
…continued
BUS
Hi-Speed USB peripheral controller
sensing.
R/W
2
0
0
© ST-NXP Wireless 2009. All rights reserved.
R/W
1
0
0
ISP1582
Table
R/W
DIR
0
0
0
29 of 67
28.