ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 46

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

ISP1582_8
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
VBUS
R/W
7
0
0
Table 62.
Bit
31 to 26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMA
R/W
6
0
0
Interrupt register: bit description
Symbol
-
EP7TX
EP7RX
EP6TX
EP6RX
EP5TX
EP5RX
EP4TX
EP4RX
EP3TX
EP3RX
EP2TX
EP2RX
EP1TX
EP1RX
EP0TX
EP0RX
-
EP0SETUP
VBUS
DMA
HS_STAT
RESUME
SUSP
PSOF
SOF
BRESET
HS_STAT
R/W
5
0
0
Rev. 08 — 22 January 2009
Description
reserved
logic 1 indicates the endpoint 7 TX buffer as interrupt source
logic 1 indicates the endpoint 7 RX buffer as interrupt source
logic 1 indicates the endpoint 6 TX buffer as interrupt source
logic 1 indicates the endpoint 6 RX buffer as interrupt source
logic 1 indicates the endpoint 5 TX buffer as interrupt source
logic 1 indicates the endpoint 5 RX buffer as interrupt source
logic 1 indicates the endpoint 4 TX buffer as interrupt source
logic 1 indicates the endpoint 4 RX buffer as interrupt source
logic 1 indicates the endpoint 3 TX buffer as interrupt source
logic 1 indicates the endpoint 3 RX buffer as interrupt source.
logic 1 indicates the endpoint 2 TX buffer as interrupt source
logic 1 indicates the endpoint 2 RX buffer as interrupt source
logic 1 indicates the endpoint 1 TX buffer as interrupt source
logic 1 indicates the endpoint 1 RX buffer as interrupt source
logic 1 indicates the endpoint 0 data TX buffer as interrupt source
logic 1 indicates the endpoint 0 data RX buffer as interrupt source
reserved
logic 1 indicates that a SETUP token was received on endpoint 0
logic 1 indicates a transition from LOW to HIGH transition on V
DMA Status: Logic 1 indicates a change in the DMA Interrupt Reason
register.
High-Speed Status: Logic 1 indicates a change from full-speed to
high-speed mode (HS connection). This bit is not set when the system
goes into full-speed suspend.
Resume Status: Logic 1 indicates that a status change from suspend
to resume (active) was detected.
Suspend Status: Logic 1 indicates that a status change from active to
suspend was detected on the bus.
Pseudo SOF Interrupt: Logic 1 indicates that a pseudo SOF or SOF
was received. Pseudo SOF is an internally generated clock signal
(full-speed: 1 ms period, high-speed: 125 s period) that is not
synchronized to the USB bus SOF or SOF.
SOF Interrupt: Logic 1 indicates that a SOF or SOF was received.
Bus Reset: Logic 1 indicates that a USB bus reset was detected.
When bit OTG in the OTG register is set, BRESET will not be set;
instead, this interrupt bit will report SE0 on DP and DM for 2 ms.
RESUME
R/W
4
0
0
SUSP
R/W
3
0
0
Hi-Speed USB peripheral controller
PSOF
R/W
2
0
0
© ST-NXP Wireless 2009. All rights reserved.
SOF
R/W
1
0
0
ISP1582
BRESET
R/W
BUS
0
0
1
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