ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 27

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

ISP1582_8
Product data sheet
Table 25.
[1]
[2]
[3]
Bit
7 to 6 -
5
4
3
2
1
0
No interrupt is designed for OTG. The V
pulsing (see note 2).
When OTG is in progress, the V
threshold or the OTG host has turned on the V
during SRP, the device must complete data-line pulsing and V
B_SESSION_VALID detection.
OTG implementation applies to the device with self-power capability. If the device works in sharing mode, it
must provide a switch circuit to supply power to the ISP1582 core during SRP.
Symbol Description
DP
BSESS
VALID
INIT
COND
DISCV
VP
OTG
OTG register: bit description
reserved
Data Pulsing: Used for data-line pulsing to toggle DP to generate the required
data-line pulsing signal. The default value of this bit is logic 0. This bit must be
cleared when data-line pulsing is completed.
B-Session Valid: The device can initiate another V
data-line pulsing and V
session valid.
This bit is latched to logic 1 once V
threshold. Once set, it remains at logic 1. To clear this bit, write logic 1. (The
ISP1582 continuously updates this bit to logic 1 when the B-session is valid. If
the B-session is valid after it is cleared, it is set back to logic 1 by the ISP1582).
0 — It implies that SRP has failed. To proceed to a normal operation, the device
can restart SRP, clear bit OTG or proceed to an error handling process.
1 — It implies that the B-session is valid. The device clears bit OTG, goes into
normal operation mode, and sets bit SOFTCT (DP pull-up) in the Mode register.
The OTG host has a maximum of 5 s before it responds to a session request.
During this period, the ISP1582 may request to suspend. Therefore, the device
firmware must wait for some time if it wishes to know the SRP result (success: if
there is minimum response from the host within 5 s; failure; if there is no
response from the host within 5 s).
Initial Condition: Write logic 1 to clear this bit. Wait for more than 2 ms and
check the bit status. If it reads logic 0, it means that V
0.8 V, and DP or DM are at SE0 during the elapsed time. The device can then
start a B-device SRP. If it reads logic 1, it means that the initial condition of SRP
is violated. So, the device must abort SRP.
The bit is set to logic 1 by the ISP1582 when initial conditions are not met, and
only writing logic 1 clears the bit. (If initial conditions are not met after this bit has
been cleared, it will be set again).
Remark: This implementation does not cover the case if an initial SRP condition
is violated when this bit is read and data-line pulsing is started.
Discharge V
before starting a new SRP. The discharge can take as long as 30 ms for V
be charged less than 0.8 V. This bit must be cleared (write logic 0) before
starting a session end detection.
V
pulsing signal. This bit must be set for more than 16 ms and must be cleared
before 26 ms.
On-The-Go:
1 — Enables the OTG function. The V
0 — Normal operation. All OTG control bits will be masked. Status bits are
undefined.
BUS
Pulsing: Used for V
Rev. 08 — 22 January 2009
[1][2][3]
BUS
BUS
: Set to logic 1 to discharge V
interrupt may be set because V
BUS
BUS
interrupt, however, may assert as a side effect during the V
BUS
pulsing, and before it clears this bit and detects a
BUS
pulsing to toggle VP to generate the required V
supply to the device. Even if the V
BUS
BUS
exceeds the B-device session valid
Hi-Speed USB peripheral controller
BUS
sensing functionality will be disabled.
pulsing before starting the
BUS
BUS
. The device discharges V
is charged over the V
BUS
BUS
discharge sequence after
© ST-NXP Wireless 2009. All rights reserved.
remains lower than
BUS
ISP1582
interrupt is found
BUS
sensing
BUS
26 of 67
BUS
BUS
BUS
to