ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 38

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Table 44.
ISP1582_8
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
DMA Command register: bit allocation
8.4.1 DMA Command register (address: 30h)
W
7
1
1
In EOT-only mode, DIS_XFER_CNT must be set to logic 1. Although the DMA transfer
counter can still be programmed, it will not have any effect on the DMA transfer. The DMA
transfer will start once the DMA command is issued. Any of the following three ways will
terminate this DMA transfer:
There are three interrupts programmable to differentiate the method of DMA termination:
bits INT_EOT, EXT_EOT and DMA_XFER_OK in the DMA Interrupt Reason register. For
details, see
Table 43.
Remark: The DMA bus defaults to 3-state, until a DMA command is executed. All the
other control signals are not 3-stated.
The DMA Command register is a 1-byte register (for bit allocation, see
initiates all DMA transfer activity on the DMA controller. The register is write-only: reading
it will return FFh.
Remark: The DMA bus will be in 3-state, until a DMA command is executed.
Table 45.
Control bits
DMA Configuration register
MODE[1:0]
WIDTH
DIS_XFER_CNT
DMA Hardware register
EOT_POL
ENDIAN[1:0]
ACK_POL, DREQ_POL,
WRITE_POL, READ_POL
Bit
7 to 0
•
•
•
Detecting an external EOT
Detecting an internal EOT (short packet on an OUT token)
Issuing a GDMA stop command
W
6
1
1
Control bits for GDMA read/write (opcode = 00h/01h)
DMA Command register: bit description
Table
Symbol
DMA_CMD[7:0]
55.
W
5
1
1
Rev. 08 — 22 January 2009
Description
determines the active read/write data strobe signals
selects the DMA bus width: 8 or 16 bits
disables the use of the DMA Transfer Counter
selects the polarity of the EOT signal
determines whether the data is to be byte swapped or
normal; applicable only in 16-bit mode
select polarity of DMA handshake signals
Description
DMA command code; see
DMA_CMD[7:0]
W
4
1
1
W
3
1
1
Hi-Speed USB peripheral controller
Table
W
2
1
1
46.
© ST-NXP Wireless 2009. All rights reserved.
W
1
1
1
Table
ISP1582
Reference
Table 49
Table 51
44) that
W
0
1
1
37 of 67