ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 66

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

21. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. ISP1582 with 3.3 V supply . . . . . . . . . . . . . . . . . .17
Fig 11. Self-powered mode . . . . . . . . . . . . . . . . . . . . . . .18
Fig 12. Bus-powered mode . . . . . . . . . . . . . . . . . . . . . . .19
Fig 13. Source differential data-to-EOP transition skew and
Fig 14. Receiver differential data jitter . . . . . . . . . . . . . . .53
Fig 15. Receiver SE0 width tolerance . . . . . . . . . . . . . . .53
Fig 16. Register access timing: separate address and data
Fig 17. ISP1582 ready signal timing . . . . . . . . . . . . . . . .54
Fig 18. GDMA mode timing (bits MODE[1:0] = 00) . . . . .55
Fig 19. GDMA mode timing (bits MODE[1:0] = 01) . . . . .56
Fig 20. GDMA mode timing (bits MODE[1:0] = 10) . . . . .56
Fig 21. EOT timing in generic processor mode . . . . . . . .57
Fig 22. Typical interface connections for generic processor
Fig 23. Load impedance for pins DP and DM (full-speed
Fig 24. Package outline SOT684-1 (HVQFN56) . . . . . . .58
Fig 25. Temperature profiles for large and small
ISP1582_8
Product data sheet
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin configuration HVQFN56 (top view) . . . . . . . . .4
Interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Behavior of bit GLINTENA . . . . . . . . . . . . . . . . . .14
Resistor and electrolytic or tantalum capacitor
needed for V
Oscilloscope reading: no resistor and capacitor in
the network . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Oscilloscope reading: with resistor and capacitor in
the network . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
POR timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Clock with respect to the external POR . . . . . . . .16
EOP width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
BUS
sensing . . . . . . . . . . . . . . . . . . .15
Rev. 08 — 22 January 2009
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