ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 45

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Table 61.
ISP1582_8
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Interrupt register: bit allocation
8.5.1 Interrupt register (address: 18h)
EP6TX
EP2TX
R/W
R/W
8.5 General registers
31
23
15
0
0
0
0
-
-
-
Table 60.
The Interrupt register consists of 4 bytes. The bit allocation is given in
When a bit is set in the Interrupt register, it indicates that the hardware condition for an
interrupt has occurred. When the Interrupt register content is nonzero, the INT output will
be asserted corresponding to the Interrupt Enable register. On detecting the interrupt, the
external microprocessor must read the Interrupt register and mask it with the
corresponding bits in the Interrupt Enable register to determine the source of the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various
bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset.
The DMA controller only has one interrupt bit: the source for a DMA interrupt is shown in
the DMA Interrupt Reason register.
Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can
be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt
Reason register, followed by writing logic 1 to the DMA bit of the Interrupt register.
Bit
15 to 13
12 to 0
EP6RX
EP2RX
R/W
R/W
30
22
14
0
0
0
0
-
-
-
Symbol
-
BURST
COUNTER
[12:0]
DMA Burst Counter register: bit description
EP5TX
EP1TX
R/W
R/W
29
21
13
0
0
0
0
-
-
-
Rev. 08 — 22 January 2009
reserved
Description
reserved
Burst Counter: This register defines the burst length. The counter must
be programmed to be a multiple of two in 16-bit mode.
The value of the burst counter must be programmed so that the burst
counter is a factor of the buffer size.
It is used to determine the assertion and deassertion of DREQ.
EP5RX
EP1RX
R/W
R/W
28
20
12
0
0
0
0
-
-
-
EP4TX
EP0TX
R/W
R/W
27
19
11
0
0
0
0
-
-
-
Hi-Speed USB peripheral controller
EP4RX
EP0RX
R/W
R/W
26
18
10
0
0
0
0
-
-
-
reserved
© ST-NXP Wireless 2009. All rights reserved.
EP7TX
EP3TX
R/W
R/W
25
17
9
0
0
0
0
Table
-
-
-
ISP1582
61.
EP0SETUP
EP7RX
EP3RX
R/W
R/W
R/W
24
16
0
0
0
0
8
0
0
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