ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 39

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Table 46.
Table 47.
ISP1582_8
Product data sheet
Code
00h
01h
02h to 0Dh -
0Eh
0Fh
10h
11h
12h
13h
14h to FFh
Bit
Symbol
DMA commands
DMA Transfer Counter register: bit allocation
Name
GDMA Read
GDMA Write
Validate Buffer Validate Buffer (for debugging only): Request from the microcontroller to validate the
Clear Buffer
-
Reset DMA
-
GDMA Stop
-
8.4.2 DMA Transfer Counter register (address: 34h)
31
This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It indicates
the remaining number of bytes left for transfer. The bit allocation is given in
For IN endpoint — Because there is a FIFO in the ISP1582 DMA controller, some data
may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and
the maximum delay time for data to be shifted to endpoint buffer is 60 ns.
For OUT endpoint — Data will not be cleared from the endpoint buffer, until all the data is
read from the DMA FIFO.
If the DMA counter is disabled in the DMA transfer, it will still decrement and rollover when
it reaches zero.
Description
Generic DMA IN token transfer: Data is transferred from the external DMA bus to the
internal buffer. Strobe: DIOW by the external DMA controller.
Generic DMA OUT token transfer: Data is transferred from the internal buffer to the external
DMA bus. Strobe: DIOR by the external DMA controller.
reserved
endpoint buffer, following a DMA-to-USB data transfer.
Clear Buffer: Request from the microcontroller to clear the endpoint buffer, after a
DMA-to-USB data transfer. Logic 1 clears the TX buffer of the indexed endpoint; the RX buffer
is not affected. The TX buffer is automatically cleared once data is sent on the USB bus. This
bit is set only when it is necessary to forcefully clear the buffer.
Remark: If using double buffer, to clear both the buffers issue the Clear Buffer command two
times, that is, set and clear this bit two times.
reserved
Reset DMA: Initializes the DMA core to its power-on reset state.
Remark: When the DMA core is reset during the Reset DMA command, the DREQ, DACK,
DIOW and DIOR handshake pins will temporarily be asserted. This can confuse the external
DMA controller. To prevent this, start the external DMA controller only after the DMA reset.
reserved
GDMA stop: This command stops the GDMA data transfer. Any data in the OUT endpoint that
is not transferred by the DMA will remain in the buffer. The FIFO data for the IN endpoint will
be written to the endpoint buffer. An interrupt bit will be set to indicate the completion of the
DMA Stop command.
Remark: For the DMA OUT transfer, if the DMA Burst Counter register is programmed to
some value, for example 512 bytes, and if a GDMA Stop command is issued in the middle of a
transfer, the transfer will continue until the end of the burst size (512 bytes). Issuing a GDMA
stop command does not allow the ISP1582 to stop in the middle of the burst. It can only be
stopped in between bursts.
reserved
30
29
Rev. 08 — 22 January 2009
DMACR4 = DMACR[31:24]
28
27
Hi-Speed USB peripheral controller
26
© ST-NXP Wireless 2009. All rights reserved.
25
ISP1582
Table
47.
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