ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 44

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Table 57.
Table 59.
ISP1582_8
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
DMA Endpoint register: bit allocation
DMA Burst Counter register: bit allocation
8.4.7 DMA Endpoint register (address: 58h)
8.4.8 DMA Burst Counter register (address: 64h)
R/W
R/W
15
7
0
0
7
7
0
0
-
-
-
-
-
-
This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA
transfers. The bit allocation is given in
Table 58.
The DMA Endpoint register must not reference the endpoint that is indexed by the
Endpoint Index register (2Ch) at any time. Doing so will result in data corruption.
Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If the
DMA Endpoint register, however, is pointed to an active endpoint, the firmware must not
reference the same endpoint on the Endpoint Index register.
Table 59
Bit
7 to 4
3 to 1
0
reserved
R/W
R/W
14
6
0
0
6
6
0
0
-
-
-
-
-
-
shows the bit allocation of the 2-byte register.
reserved
DMA Endpoint register: bit description
Symbol
-
EPIDX[2:0]
DMADIR
R/W
R/W
13
5
0
0
5
5
0
0
-
-
-
-
-
-
Rev. 08 — 22 January 2009
Description
reserved
Endpoint Index: Selects the indicated endpoint for DMA access
DMA Direction:
0 — Selects the RX/OUT FIFO for DMA read transfers
1 — Selects the TX/IN FIFO for DMA write transfers
BURSTCOUNTER[7:0]
R/W
R/W
R/W
12
4
0
0
4
0
0
4
0
0
-
-
-
reserved
Table
R/W
R/W
R/W
R/W
57.
11
3
0
0
3
0
0
0
0
3
0
0
BURSTCOUNTER[12:8]
Hi-Speed USB peripheral controller
EPIDX[2:0]
R/W
R/W
R/W
R/W
10
2
0
0
2
0
0
0
0
2
0
0
© ST-NXP Wireless 2009. All rights reserved.
R/W
R/W
R/W
R/W
1
0
0
1
0
0
9
0
0
1
1
1
ISP1582
DMADIR
R/W
R/W
R/W
R/W
0
0
0
0
0
0
8
0
0
0
0
0
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