ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 41

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Table 51.
ISP1582_8
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
DMA Hardware register: bit allocation
8.4.4 DMA Hardware register (address: 3Ch)
R/W
7
0
0
ENDIAN[1:0]
Table 50.
[1]
The DMA Hardware register consists of 1 byte. The bit allocation is shown in
This register determines the polarity of bus control signals (EOT, DACK, DREQ, DIOR
and DIOW). It also controls whether the upper and lower parts of the data bus are
swapped (bits ENDIAN[1:0]).
Bit
15 to 8
7
6 to 4
3 to 2
1
0
The DREQ pin will be driven only after performing a write access to the DMA Configuration register (that is,
after configuring the DMA Configuration register).
R/W
6
0
0
Symbol
-
DIS_XFER_CNT Disable Transfer Count: Logic 1 disables the DMA Transfer
-
MODE[1:0]
-
WIDTH
DMA Configuration register: bit description
EOT_POL
R/W
5
0
0
Rev. 08 — 22 January 2009
Description
reserved
Counter (see
reserved
Mode: These bits affect GDMA handshake signals.
00 — DIOW strobes data from the DMA bus into the ISP1582; DIOR
puts data from the ISP1582 on the DMA bus.
01 — DACK strobes data from the DMA bus into the ISP1582; DIOR
puts data from the ISP1582 on the DMA bus.
10 — DACK strobes data from the DMA bus into the ISP1582 and
also puts data from the ISP1582 on the DMA bus.
11 — reserved
reserved
Width: This bit selects the DMA bus width.
0 — 8-bit data bus
1 — 16-bit data bus
reserved
4
-
-
-
[1]
Table
ACK_POL
R/W
47).
3
0
0
Hi-Speed USB peripheral controller
DREQ_
POL
R/W
2
1
1
WRITE_
© ST-NXP Wireless 2009. All rights reserved.
POL
R/W
1
0
0
ISP1582
Table
READ_
POL
R/W
0
0
0
40 of 67
51.