ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 17

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ISP1582BS,557

Manufacturer Part Number
ISP1582BS,557
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ISP1582BS,557

Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
56
Lead Free Status / RoHS Status
Compliant
ISP1582_8
Product data sheet
7.15 Power supply
The RESET_N pin can either be connected to V
externally controlled (by the microcontroller, ASIC, and so on). When V
connected to the RESET_N pin, the internal pulse width t
The power-on reset function can be explained by viewing the dips at t2 to t3 and t4 to t5
on the V
t0 — The internal POR starts with a HIGH level.
t1 — The detector will see the passing of the trip level and a delay element will add
another t
t2-t3 — The internal POR pulse will be generated whenever V
more than 11 s.
t4-t5 — The dip is too short (< 11 s) and the internal POR pulse will not react and will
remain LOW.
Figure 9
The ISP1582 can be powered by 3.3 V
If the ISP1582 is powered by V
provides a 1.8 V supply voltage for the internal logic.
Fig 8.
Fig 9.
t0
CC(POR)
PORP
shows the availability of the clock with respect to the external POR.
(1) PORP = Power-On Reset Pulse.
POR timing
Power on V
Stable external clock is to be available at B.
The ISP1582 is operational at C.
Clock with respect to the external POR
RESET_N
t1
before it drops to LOW.
t
external
PORP
curve
clock
V
CC
CC
at A.
Rev. 08 — 22 January 2009
(Figure
8).
A
CC
= 3.3 V, an integrated 3.3 V-to-1.8 V voltage regulator
500 s
t2
0.3 V. For connection details, see
B
2 ms
t3
CC
t
PORP
(using the internal POR circuit) or
Hi-Speed USB peripheral controller
PORP
t4
C
CC(POR)
will typically be 200 ns.
t5
© ST-NXP Wireless 2009. All rights reserved.
004aaa927
drops below V
CC
ISP1582
is directly
Figure
004aab162
V
PORP
V
CC(POR)
trip
(1)
10.
16 of 67
trip
for

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