ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 65

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

20. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Operation truth table for OTG . . . . . . . . . . . . .19
Table 11. Operation truth table for SoftConnect . . . . . . .19
Table 12. Operation truth table for clock off during
Table 13. Operation truth table for back voltage
Table 14. Operation truth table for OTG . . . . . . . . . . . . .20
Table 15. Register overview . . . . . . . . . . . . . . . . . . . . . .21
Table 16. Address register: bit allocation . . . . . . . . . . . .23
Table 17. Address register: bit description . . . . . . . . . . .23
Table 18. Mode register: bit allocation . . . . . . . . . . . . . . .23
Table 19. Mode register: bit description . . . . . . . . . . . . .23
Table 20. Status of the chip . . . . . . . . . . . . . . . . . . . . . . .24
Table 21. Interrupt Configuration register: bit allocation .25
Table 22. Interrupt Configuration register: bit description 25
Table 23. Debug mode settings . . . . . . . . . . . . . . . . . . . .25
Table 24. OTG register: bit allocation . . . . . . . . . . . . . . .25
Table 25. OTG register: bit description . . . . . . . . . . . . . .26
Table 26. Interrupt Enable register: bit allocation . . . . . .28
Table 27. Interrupt Enable register: bit description . . . . .28
Table 28. Endpoint Index register: bit allocation . . . . . . .29
Table 29. Endpoint Index register: bit description . . . . . .30
Table 30. Addressing of endpoint buffers . . . . . . . . . . . .30
Table 31. Control Function register: bit allocation . . . . . .30
Table 32. Control Function register: bit description . . . . .31
Table 33. Data Port register: bit allocation . . . . . . . . . . . .32
Table 34. Data Port register: bit description . . . . . . . . . .32
Table 35. Buffer Length register: bit allocation . . . . . . . .33
Table 36. Buffer Length register: bit description . . . . . . .33
Table 37. Buffer Status register: bit allocation . . . . . . . . .34
Table 38. Buffer Status register: bit description . . . . . . . .34
Table 39. Endpoint MaxPacketSize register: bit
Table 40. Endpoint MaxPacketSize register: bit
Table 41. Endpoint Type register: bit allocation . . . . . . . .35
Table 42. Endpoint Type register: bit description . . . . . . .36
Table 43. Control bits for GDMA read/write (opcode =
Table 44. DMA Command register: bit allocation . . . . . .37
Table 45. DMA Command register: bit description . . . . .37
Table 46. DMA commands . . . . . . . . . . . . . . . . . . . . . . .38
Table 47. DMA Transfer Counter register: bit allocation .38
Table 48. DMA Transfer Counter register: bit description 39
Table 49. DMA Configuration register: bit allocation . . . .39
ISP1582_8
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Endpoint access and programmability . . . . . . . .8
ISP1582 pin status . . . . . . . . . . . . . . . . . . . . . . 11
ISP1582 output status . . . . . . . . . . . . . . . . . . .12
Power modes . . . . . . . . . . . . . . . . . . . . . . . . . .17
Operation truth table for SoftConnect . . . . . . .18
Operation truth table for clock off during
suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Operation truth table for back voltage
compliance . . . . . . . . . . . . . . . . . . . . . . . . . . .18
suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
compliance . . . . . . . . . . . . . . . . . . . . . . . . . . .20
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
00h/01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Rev. 08 — 22 January 2009
Table 50. DMA Configuration register: bit description . . 40
Table 51. DMA Hardware register: bit allocation . . . . . . 40
Table 52. DMA Hardware register: bit description . . . . . 41
Table 53. DMA Interrupt Reason register: bit allocation . 41
Table 54. DMA Interrupt Reason register: bit description 42
Table 55. Internal EOT-functional relation with bit
Table 56. DMA Interrupt Enable register: bit allocation . 42
Table 57. DMA Endpoint register: bit allocation . . . . . . . 43
Table 58. DMA Endpoint register: bit description . . . . . . 43
Table 59. DMA Burst Counter register: bit allocation . . . 43
Table 60. DMA Burst Counter register: bit description . . 44
Table 61. Interrupt register: bit allocation . . . . . . . . . . . . 44
Table 62. Interrupt register: bit description . . . . . . . . . . . 45
Table 63. Chip ID register: bit allocation . . . . . . . . . . . . . 46
Table 64. Chip ID register: bit description . . . . . . . . . . . . 46
Table 65. Frame Number register: bit allocation . . . . . . . 46
Table 66. Frame Number register: bit description . . . . . . 47
Table 67. Scratch register: bit allocation . . . . . . . . . . . . . 47
Table 68. Scratch register: bit description . . . . . . . . . . . . 47
Table 69. Unlock Device register: bit allocation . . . . . . . 47
Table 70. Unlock Device register: bit description . . . . . . 48
Table 71. Test Mode register: bit allocation . . . . . . . . . . 48
Table 72. Test Mode register: bit description . . . . . . . . . 48
Table 73. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 74. Recommended operating conditions . . . . . . . 49
Table 75. Static characteristics: supply pins . . . . . . . . . . 49
Table 76. Static characteristics: digital pins . . . . . . . . . . 50
Table 77. Static characteristics: OTG detection . . . . . . . 50
Table 78. Static characteristics: analog I/O pins DP and
Table 79. Dynamic characteristics . . . . . . . . . . . . . . . . . 51
Table 80. Dynamic characteristics: analog I/O pins DP and
Table 81. Register access timing parameters: separate
Table 82. GDMA mode timing parameters . . . . . . . . . . . 55
Table 83. SnPb eutectic process (from J-STD-020C) . . . 60
Table 84. Lead-free process (from J-STD-020C) . . . . . . 60
Table 85. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 86. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 63
DMA_XFER_OK . . . . . . . . . . . . . . . . . . . . . . . 42
DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
address and data buses . . . . . . . . . . . . . . . . . 53
Hi-Speed USB peripheral controller
© ST-NXP Wireless 2009. All rights reserved.
ISP1582
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