ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 37

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

ISP1582_8
Product data sheet
8.4 DMA registers
Table 42.
The Generic DMA (GDMA) transfer can be done by writing the proper opcode in the DMA
Command register. Control bits are given in
GDMA read/write (opcode = 00h/01h) for GDMA mode: Depending on the MODE[1:0]
bits set in the DMA configuration register, the DACK, DIOR or DIOW signal strobes data.
These signals are driven by the external DMA controller.
GDMA mode can operate in either counter mode or EOT-only mode.
In counter mode, bit DIS_XFER_CNT in the DMA Configuration register must be set to
logic 0. The DMA Transfer Counter register must be programmed before any DMA
command is issued. The DMA transfer counter is set by writing from the LSByte to the
MSByte (address: 34h to 37h). The DMA transfer count is internally updated only after the
MSByte is written. Once the DMA transfer is started, the transfer counter starts
decrementing and on reaching 0, bit DMA_XFER_OK is set and an interrupt is generated
by the ISP1582. If the DMA master wishes to terminate the DMA transfer, it can issue an
EOT signal to the ISP1582. This EOT signal overrides the transfer counter and can
terminate the DMA transfer at any time.
Bit
15 to 5
4
3
2
1 to 0
Symbol
-
NOEMPKT
ENABLE
DBLBUF
ENDPTYP[1:0]
Endpoint Type register: bit description
Rev. 08 — 22 January 2009
Description
reserved
No Empty Packet: Logic 0 causes the ISP1582 to return a null length
packet for the IN token after the DMA IN transfer is complete. For the
IN DMA transfer, which does not require a null length packet after DMA
completion, set to logic 1 to disable the generation of the null length
packet.
Endpoint Enable: Logic 1 enables the FIFO of the indexed endpoint.
The memory size is allocated as specified in the Endpoint
MaxPacketSize register. Logic 0 disables the FIFO.
Remark: Stalling a data endpoint will confuse the Data Toggle bit on
the stalled endpoint because the internal logic picks up from where it
has stalled. Therefore, the Data Toggle bit must be reset by disabling
and re-enabling the corresponding endpoint (by setting bit ENABLE to
logic 0 or logic 1 in the Endpoint Type register) to reset the PID.
Double Buffering: Logic 1 enables double buffering for the indexed
endpoint. Logic 0 disables double buffering.
Remark: When performing a write to two empty buffers, ensure that a
minimum of 200 ns delay is provided from the last write of the first
buffer to the first write of the second buffer. Otherwise, the first few
data bytes may not be written to the second buffer, causing data
corruption.
Endpoint Type: These bits select the endpoint type as follows.
00 — Not used
01 — Isochronous
10 — Bulk
11 — Interrupt
Table
43.
Hi-Speed USB peripheral controller
© ST-NXP Wireless 2009. All rights reserved.
ISP1582
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