ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 13

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

ISP1582_8
Product data sheet
7.12.1 Interrupt output pin
7.12 Interrupt
Table 5
conditions.
Table 5.
[1]
[2]
The Interrupt Configuration register of the ISP1582 controls the behavior of the INT output
pin. The polarity and signaling mode of pin INT can be programmed by setting bits
INTPOL and INTLVL of the Interrupt Configuration register (R/W: 10h); see
GLINTENA of the Mode register (R/W: 0Ch) is used to enable pin INT. Default settings
after reset are active LOW and level mode. When pulse mode is selected, a pulse of 60 ns
is generated when the OR-ed combination of all interrupt bits changes from logic 0 to
logic 1.
Figure 3
Each of the indicated USB and DMA events is logged in a status bit of the Interrupt
register and the DMA Interrupt Reason register, respectively. Corresponding bits in the
Interrupt Enable register and the DMA Interrupt Enable register determine whether an
event will generate an interrupt.
Interrupts can be masked globally by means of bit GLINTENA of the Mode register; see
Table
Field CDBGMOD[1:0] of the Interrupt Configuration register controls the generation of INT
signals for the control pipe. Field DDBGMODIN[1:0] of the Interrupt Configuration register
controls the generation of INT signals for the IN pipe. Field DDBGMODOUT[1:0] of the
Interrupt Configuration register controls the generation of INT signals for the OUT pipe;
see
V
0 V
3.3 V
3.3 V
CC
Dead: The USB cable is plugged out, and V
X: Don’t care.
Table
19.
illustrates the behavior of output pins with V
shows the relationship between interrupt events and pin INT.
23.
ISP1582 output status
Rev. 08 — 22 January 2009
V
0 V
V
V
CC(I/O)
CC
CC
CC(I/O)
State
dead
reset
after reset
is not available.
[1]
CC(I/O)
Hi-Speed USB peripheral controller
and V
INT
X
HIGH
HIGH
[2]
CC
© ST-NXP Wireless 2009. All rights reserved.
in various operating
ISP1582
SUSPEND
X
LOW
LOW
Table
[2]
22. Bit
12 of 67