ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 43

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Table 56.
ISP1582_8
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
DMA Interrupt Enable register: bit allocation
8.4.6 DMA Interrupt Enable register (address: 54h)
TEST4
15
R
7
-
-
-
-
-
Table 54.
Table 55.
This 2-byte register controls the interrupt generation of the source bits in the DMA
Interrupt Reason register. The bit allocation is given in
given in
Logic 1 enables the interrupt generation. After a bus reset, interrupt generation is
disabled, with the values turning to logic 0.
Bit
15
14 to 13 -
12
11
10
9
8
7 to 0
INT_EOT
1
1
0
14
6
-
-
-
-
-
-
Table
Symbol
TEST3
GDMA_STOP
EXT_EOT
INT_EOT
-
DMA_XFER_OK DMA Transfer OK: Logic 1 indicates that the DMA transfer is
-
reserved
DMA Interrupt Reason register: bit description
Internal EOT-functional relation with bit DMA_XFER_OK
DMA_XFER_OK
0
1
1
54.
13
5
-
-
-
-
-
-
Rev. 08 — 22 January 2009
Description
This bit is set when the DMA transfer for a packet (OUT transfer)
terminates before the whole packet has been transferred. This bit is
a status bit, and the corresponding mask bit of this register is always
logic 0. Writing any value other than logic 0 has no effect.
reserved
GDMA Stop: When the GDMA_STOP command is issued to DMA
Command registers, it means the DMA transfer has successfully
terminated.
External EOT: Logic 1 indicates that an external EOT is detected.
Internal EOT: Logic 1 indicates that an internal EOT is detected; see
Table
reserved
completed (DMA Transfer Counter has become zero).
reserved
IE_GDMA_
Description
During the DMA transfer, there is a premature termination with
short packet.
DMA transfer is completed with short packet and the DMA
transfer counter has reached 0.
DMA transfer is completed without any short packet and the DMA
transfer counter has reached 0.
STOP
R/W
12
55.
4
0
0
-
-
-
reserved
IE_EXT_
EOT
R/W
11
3
0
0
-
-
-
Hi-Speed USB peripheral controller
IE_INT_
Table
EOT
R/W
10
2
0
0
-
-
-
56. The bit description is
reserved
© ST-NXP Wireless 2009. All rights reserved.
R/W
1
9
0
0
-
-
-
ISP1582
XFER_OK
IE_DMA_
R/W
0
8
0
0
-
-
-
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