ISP1582BS,557 NXP Semiconductors, ISP1582BS,557 Datasheet - Page 25

• Manufacturer Part Number: ISP1582BS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1582BS,557

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Table 20.
ISP1582_8
Product data sheet
V
On
Off
BUS
SoftConnect = on
pull-up resistor on pin DP
pull-up resistor on pin DP is present; suspend
interrupt is generated after 3 ms of no bus activity
Status of the chip
8.2.3 Interrupt Configuration register (address: 10h)
Table 19.
The status of the chip is shown in
This 1-byte register determines the behavior and polarity of the INT output. The bit
allocation is shown in
or NYET, it will generate interrupts, depending on three Debug mode fields.
Bit
7
6
5
4
3
2
1
0
Symbol
CLKAON
SNDRSU
GOSUSP
SFRESET
GLINTENA
WKUPCS
PWRON
SOFTCT
Mode register: bit description
Rev. 08 — 22 January 2009
Table
Description
Clock Always On: Logic 1 indicates that internal clocks are always
running when in the suspend state. Logic 0 switches off the internal
oscillator and PLL when the device goes into suspend mode. The
device will consume less power if this bit is set to logic 0. The clock is
stopped about 2 ms after bit GOSUSP is set and then cleared.
Send Resume: Writing logic 1, followed by logic 0 will generate a 10 ms
upstream resume signal.
Remark: The upstream resume signal is generated 5 ms after this bit is
set to logic 0.
Go Suspend: Writing logic 1, followed by logic 0 will activate suspend
mode.
Soft Reset: Writing logic 1, followed by logic 0 will enable a
software-initiated reset to the ISP1582. A soft reset is similar to a
hardware-initiated reset (using pin RESET_N).
Global Interrupt Enable: Logic 1 enables all interrupts. Individual
interrupts can be masked by clearing the corresponding bits in the
Interrupt Enable register.
When this bit is not set, an unmasked interrupt will not generate an
interrupt trigger on the interrupt pin. If global interrupt, however, is
enabled while there is any pending unmasked interrupt, an interrupt
signal will be immediately generated on the interrupt pin. (If the interrupt
is set to pulse mode, the interrupt events that were generated before the
global interrupt is enabled will not appear on the interrupt pin).
Wake Up On Chip Select: Logic 1 enables wake-up from suspend
mode through a valid register read on the ISP1582. (A read will invoke
the chip clock to restart. If you write to the register before the clock gets
stable, it may cause malfunctioning).
Power On: The SUSPEND pin output control.
0 — The SUSPEND pin is HIGH when the ISP1582 is in the suspend
state. Otherwise, the SUSPEND pin is LOW.
1 — When the device is woken up from the suspend state, there will be
a 1 ms active HIGH pulse on the SUSPEND pin. The SUSPEND pin will
remain LOW in all other states.
SoftConnect: Logic 1 enables the connection of the 1.5 k pull-up
resistor on pin RPU to the DP pin.
21. When the USB SIE receives or generates an ACK, NAK
SoftConnect = off
pull-up resistor on pin DP is removed; suspend interrupt is
generated after 3 ms of no bus activity
pull-up resistor on pin DP is removed; suspend interrupt is
generated after 3 ms of no bus activity
Table
…continued
20.
Hi-Speed USB peripheral controller
© ST-NXP Wireless 2009. All rights reserved.
ISP1582
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