MT29F4G08ABADAWP:D Micron Technology Inc, MT29F4G08ABADAWP:D Datasheet - Page 7

• Manufacturer Part Number: MT29F4G08ABADAWP:D
• Description: MICMT29F4G08ABADAWP:D 4GB SLC NAND 34NM
• Manufacturer: Micron Technology Inc

Specifications of MT29F4G08ABADAWP:D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Micron Confidential and Proprietary
4Gb, 8Gb: x8, x16 NAND Flash Memory
Features
Figure 51: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) ................... 79
Figure 52: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ....................................................... 80
Figure 53: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled ........... 80
Figure 54: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation ....................................................... 80
Figure 55: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................. 81
Figure 56: PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) Operation ................................... 81
Figure 57: Flash Array Protected: Invert Area Bit = 0 ........................................................................................ 83
Figure 58: Flash Array Protected: Invert Area Bit = 1 ........................................................................................ 83
Figure 59: UNLOCK Operation ...................................................................................................................... 84
Figure 60: LOCK Operation ............................................................................................................................ 85
Figure 61: LOCK TIGHT Operation ................................................................................................................ 86
Figure 62: PROGRAM/ERASE Issued to Locked Block ..................................................................................... 87
Figure 63: BLOCK LOCK READ STATUS ......................................................................................................... 87
Figure 64: BLOCK LOCK Flowchart ................................................................................................................ 88
Figure 65: OTP DATA PROGRAM (After Entering OTP Operation Mode) .......................................................... 91
Figure 66: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation
Mode) ........................................................................................................................................................ 92
Figure 67: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) ................................................ 93
Figure 68: OTP DATA READ .......................................................................................................................... 94
Figure 69: OTP DATA READ with RANDOM DATA READ Operation ................................................................ 95
Figure 70: TWO-PLANE PAGE READ .............................................................................................................. 97
Figure 71: TWO-PLANE PAGE READ with RANDOM DATA READ ................................................................... 98
Figure 72: TWO-PLANE PROGRAM PAGE ...................................................................................................... 98
Figure 73: TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT .......................................................... 99
Figure 74: TWO-PLANE PROGRAM PAGE CACHE MODE .............................................................................. 100
Figure 75: TWO-PLANE INTERNAL DATA MOVE .......................................................................................... 101
Figure 76: TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ ........................... 102
Figure 77: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT .............................................. 103
Figure 78: TWO-PLANE BLOCK ERASE ......................................................................................................... 104
Figure 79: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle ....................................................................... 104
Figure 80: Spare Area Mapping (x8) ............................................................................................................... 108
Figure 81: Spare Area Mapping (x16) ............................................................................................................. 109
Figure 82: RESET Operation ......................................................................................................................... 118
Figure 83: READ STATUS Cycle ..................................................................................................................... 118
Figure 84: READ STATUS ENHANCED Cycle ................................................................................................. 119
Figure 85: READ PARAMETER PAGE ............................................................................................................. 119
Figure 86: READ PAGE ................................................................................................................................. 120
Figure 87: READ PAGE Operation with CE# “Don’t Care” ............................................................................... 121
Figure 88: RANDOM DATA READ ................................................................................................................. 122
Figure 89: READ PAGE CACHE SEQUENTIAL ................................................................................................ 123
Figure 90: READ PAGE CACHE RANDOM ..................................................................................................... 124
Figure 91: READ ID Operation ...................................................................................................................... 125
Figure 92: PROGRAM PAGE Operation .......................................................................................................... 125
Figure 93: PROGRAM PAGE Operation with CE# “Don’t Care” ....................................................................... 126
Figure 94: PROGRAM PAGE Operation with RANDOM DATA INPUT ............................................................. 126
Figure 95: PROGRAM PAGE CACHE .............................................................................................................. 127
Figure 96: PROGRAM PAGE CACHE Ending on 15h ....................................................................................... 127
Figure 97: INTERNAL DATA MOVE ............................................................................................................... 128
Figure 98: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ...................................................... 128
Figure 99: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled ................ 129
Figure 100: ERASE BLOCK Operation ............................................................................................................ 129
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m60a_4gb_nand.pdf – Rev. G 11/10 EN
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